Created first 3 blogposts from old website

content/posts/mimasfirmware-02.md

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+title = "Mimas PC-FPGA interface with Wishbone master"
+tags = ["Embedded", "FPGA", "Wishbone"]
+date = "2022-09-10"
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+
+[View project on github](https://github.com/Jojojoppe/MimasV1Firmware)
+
+With the created [PC-FPGA interface for the Mimas Spartan 6]({{< ref "/posts/mimasfirmware-01" >}}) development board, it was time to do something useful with it. I decided to make a Wishbone (version 4 pipelined) bus master which is controlled by the USB interface. This "Hardware-Firmware (HF) to Wishbone" interface can be connected to one of the HF interface channels and uses one transfer (one byte) for communicating a command and a multiple of four transfers (four bytes) for address and data transfers.
+
+| ![System layout](/images/blog/mimas/wb_bridge.png) |
+|:--:| 
+| *System layout* |
+
+### Bus Reset
+
+The first command is the reset command (`CMD=0x00`) which brings the wishbone bus state back to idle. The issuer must wait for the first valid transaction on that channel and check if a valid response code is transfered (`A0`, an error is indicated with return code `AF`).
+
+| ![HF side of bus reset](/images/blog/mimas/hfreset.png) |
+|:--:| 
+| *HF side of bus reset* |
+
+### Bus Write
+
+The second command is the write command (`CMD=0x01`) which requires an address and data word. After the transfers of the address and data bytes, the wishbone write transaction is activated. The issuer must wait for the first valid transaction on that channel and check if a valid response code is transferred (`A0`, an error is indicated with return code `AF`).
+
+| ![HF side of bus write](/images/blog/mimas/hfwrite.png) |
+|:--:| 
+| *HF side of bus write* |
+
+### Bus Read
+
+The third command is the read command (`CMD=0x02`) which requires an address. After the transfers of the address bytes, the wishbone read transaction is activated. The issuer must wait for the first valid transaction on that channel and read in 4 subsequent bytes which will contain the read-back data. Then the issuer must read one last transaction and check if a valid response code is transferred (`A0`, an error is indicated with return code `AF`).
+
+| ![HF side of bus read](/images/blog/mimas/hfread.png) |
+|:--:| 
+| *HF side of bus read* |