51 lines
1.4 KiB
VHDL
51 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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generic (
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-- Formal generic is used to embed formal validation stuff
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formal : boolean := false;
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-- Data width
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width : integer := 16;
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-- Max count
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mxcnt : integer := 256
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);
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port (
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ACLK : in std_logic;
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ARESETN : in std_logic;
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cnt : out std_logic_vector(width-1 downto 0)
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);
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end entity;
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architecture behav of counter is
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signal icnt : unsigned (width-1 downto 0);
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begin
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cnt <= std_logic_vector(icnt);
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f_counter : if formal generate
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begin
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-- Set clock source for all assertions
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default clock is rising_edge(ACLK);
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-- Counter is always under mxcnt if it started under max
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a_never_exceeds_max : assert (always (icnt<mxcnt) -> always (icnt<mxcnt));
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-- Counter is always reset to 0
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a_counter_reset_to_zero : assert (always (ARESETN='0') -> (icnt=0));
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end generate;
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p_counter : process(ACLK, ARESETN)
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begin
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if ARESETN='0' then
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icnt <= (others=>'0');
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elsif rising_edge(ACLK) then
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-- Without this -1 the assertion wont hold
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if icnt<mxcnt-1 then
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icnt <= icnt + 1;
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else
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icnt <= (others=>'0');
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end if;
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end if;
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end process;
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end architecture; |