367 lines
20 KiB
Tcl
367 lines
20 KiB
Tcl
############################################################################
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##
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## Xilinx, Inc. 2006 www.xilinx.com
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############################################################################
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## File name : ps7_constraints.xdc
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##
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## Details : Constraints file
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## FPGA family: zynq
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## FPGA: xc7z010clg400-2
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## Device Size: xc7z010
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## Package: clg400
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## Speedgrade: -2
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##
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##
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############################################################################
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############################################################################
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############################################################################
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# Clock constraints #
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############################################################################
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create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
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set_input_jitter clk_fpga_0 0.3
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#The clocks are asynchronous, user should constrain them appropriately.#
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############################################################################
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# I/O STANDARDS and Location Constraints #
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############################################################################
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# UART 1 / rx / MIO[45]
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set_property iostandard "LVCMOS33" [get_ports "MIO[45]"]
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set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
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set_property slew "slow" [get_ports "MIO[45]"]
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set_property drive "8" [get_ports "MIO[45]"]
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set_property pullup "TRUE" [get_ports "MIO[45]"]
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set_property PIO_DIRECTION "INPUT" [get_ports "MIO[45]"]
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# UART 1 / tx / MIO[44]
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set_property iostandard "LVCMOS33" [get_ports "MIO[44]"]
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set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
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set_property slew "slow" [get_ports "MIO[44]"]
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set_property drive "8" [get_ports "MIO[44]"]
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set_property pullup "TRUE" [get_ports "MIO[44]"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[44]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
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set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
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set_property slew "FAST" [get_ports "DDR_VRP"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
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set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
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set_property slew "FAST" [get_ports "DDR_VRN"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
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set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
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set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
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set_property slew "SLOW" [get_ports "DDR_WEB"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
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set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
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set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
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set_property slew "SLOW" [get_ports "DDR_RAS_n"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
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set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
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set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
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set_property slew "SLOW" [get_ports "DDR_ODT"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
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set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
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set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
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set_property slew "FAST" [get_ports "DDR_DRSTB"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
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set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
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set_property slew "FAST" [get_ports "DDR_DQS[3]"]
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set_property pullup "TRUE" [get_ports "DDR_DQS[3]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
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set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
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set_property slew "FAST" [get_ports "DDR_DQS[2]"]
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set_property pullup "TRUE" [get_ports "DDR_DQS[2]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
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set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
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set_property slew "FAST" [get_ports "DDR_DQS[1]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
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set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
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set_property slew "FAST" [get_ports "DDR_DQS[0]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
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set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
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set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
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set_property pullup "TRUE" [get_ports "DDR_DQS_n[3]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
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set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
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set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
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set_property pullup "TRUE" [get_ports "DDR_DQS_n[2]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
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set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
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set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
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set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
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set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
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set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
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set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
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set_property slew "FAST" [get_ports "DDR_DQ[9]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
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set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
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set_property slew "FAST" [get_ports "DDR_DQ[8]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
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set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
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set_property slew "FAST" [get_ports "DDR_DQ[7]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
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set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
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set_property slew "FAST" [get_ports "DDR_DQ[6]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
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set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
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set_property slew "FAST" [get_ports "DDR_DQ[5]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
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set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
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set_property slew "FAST" [get_ports "DDR_DQ[4]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
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set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
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set_property slew "FAST" [get_ports "DDR_DQ[3]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
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set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
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set_property slew "FAST" [get_ports "DDR_DQ[31]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[31]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
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set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
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set_property slew "FAST" [get_ports "DDR_DQ[30]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[30]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
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set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
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set_property slew "FAST" [get_ports "DDR_DQ[2]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
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set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
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set_property slew "FAST" [get_ports "DDR_DQ[29]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[29]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
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set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
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set_property slew "FAST" [get_ports "DDR_DQ[28]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[28]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
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set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
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set_property slew "FAST" [get_ports "DDR_DQ[27]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[27]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
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set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
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set_property slew "FAST" [get_ports "DDR_DQ[26]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[26]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
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set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
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set_property slew "FAST" [get_ports "DDR_DQ[25]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[25]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
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set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
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set_property slew "FAST" [get_ports "DDR_DQ[24]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[24]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
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set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
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set_property slew "FAST" [get_ports "DDR_DQ[23]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[23]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
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set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
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set_property slew "FAST" [get_ports "DDR_DQ[22]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[22]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
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set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
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set_property slew "FAST" [get_ports "DDR_DQ[21]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[21]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
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set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
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set_property slew "FAST" [get_ports "DDR_DQ[20]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[20]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
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set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
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set_property slew "FAST" [get_ports "DDR_DQ[1]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
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set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
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set_property slew "FAST" [get_ports "DDR_DQ[19]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[19]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
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set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
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set_property slew "FAST" [get_ports "DDR_DQ[18]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[18]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
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set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
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set_property slew "FAST" [get_ports "DDR_DQ[17]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[17]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
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set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
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set_property slew "FAST" [get_ports "DDR_DQ[16]"]
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set_property pullup "TRUE" [get_ports "DDR_DQ[16]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
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set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
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set_property slew "FAST" [get_ports "DDR_DQ[15]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
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set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
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set_property slew "FAST" [get_ports "DDR_DQ[14]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
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set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
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set_property slew "FAST" [get_ports "DDR_DQ[13]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
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set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
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set_property slew "FAST" [get_ports "DDR_DQ[12]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
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set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
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set_property slew "FAST" [get_ports "DDR_DQ[11]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
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set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
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set_property slew "FAST" [get_ports "DDR_DQ[10]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
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set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
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set_property slew "FAST" [get_ports "DDR_DQ[0]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
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set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
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set_property slew "FAST" [get_ports "DDR_DM[3]"]
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set_property pullup "TRUE" [get_ports "DDR_DM[3]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
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set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
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set_property slew "FAST" [get_ports "DDR_DM[2]"]
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set_property pullup "TRUE" [get_ports "DDR_DM[2]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
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set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
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set_property slew "FAST" [get_ports "DDR_DM[1]"]
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
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set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
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set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
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set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
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set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
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set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
|
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set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
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set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
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set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
|
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set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
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set_property slew "SLOW" [get_ports "DDR_CKE"]
|
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
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set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
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set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
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set_property slew "FAST" [get_ports "DDR_Clk"]
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set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
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set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
|
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set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
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set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
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set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
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set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
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set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
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set_property slew "SLOW" [get_ports "DDR_CAS_n"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
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|
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
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set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
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set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
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set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
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set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
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set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
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set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
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set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
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set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
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set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
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set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
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set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
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set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
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set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
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set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
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set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
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set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
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set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
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set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
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|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
|
|
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
|
|
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
|
|
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
|
|
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
|
|
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
|
|
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
|
|
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
|
|
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
|
|
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
|
|
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
|
|
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
|
|
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
|
|
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
|
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
|
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
|
|
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
|
|
set_property slew "fast" [get_ports "PS_PORB"]
|
|
set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"]
|
|
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
|
|
set_property slew "fast" [get_ports "PS_SRSTB"]
|
|
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
|
|
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
|
|
set_property slew "fast" [get_ports "PS_CLK"]
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