88 lines
4.1 KiB
Verilog
88 lines
4.1 KiB
Verilog
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:processing_system7:5.5
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// IP Revision: 6
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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zynqps your_instance_name (
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.FCLK_CLK0(FCLK_CLK0), // output wire FCLK_CLK0
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.FCLK_RESET0_N(FCLK_RESET0_N), // output wire FCLK_RESET0_N
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.MIO(MIO), // inout wire [53 : 0] MIO
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.DDR_CAS_n(DDR_CAS_n), // inout wire DDR_CAS_n
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.DDR_CKE(DDR_CKE), // inout wire DDR_CKE
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.DDR_Clk_n(DDR_Clk_n), // inout wire DDR_Clk_n
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.DDR_Clk(DDR_Clk), // inout wire DDR_Clk
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.DDR_CS_n(DDR_CS_n), // inout wire DDR_CS_n
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.DDR_DRSTB(DDR_DRSTB), // inout wire DDR_DRSTB
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.DDR_ODT(DDR_ODT), // inout wire DDR_ODT
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.DDR_RAS_n(DDR_RAS_n), // inout wire DDR_RAS_n
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.DDR_WEB(DDR_WEB), // inout wire DDR_WEB
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.DDR_BankAddr(DDR_BankAddr), // inout wire [2 : 0] DDR_BankAddr
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.DDR_Addr(DDR_Addr), // inout wire [14 : 0] DDR_Addr
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.DDR_VRN(DDR_VRN), // inout wire DDR_VRN
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.DDR_VRP(DDR_VRP), // inout wire DDR_VRP
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.DDR_DM(DDR_DM), // inout wire [3 : 0] DDR_DM
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.DDR_DQ(DDR_DQ), // inout wire [31 : 0] DDR_DQ
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.DDR_DQS_n(DDR_DQS_n), // inout wire [3 : 0] DDR_DQS_n
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.DDR_DQS(DDR_DQS), // inout wire [3 : 0] DDR_DQS
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.PS_SRSTB(PS_SRSTB), // inout wire PS_SRSTB
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.PS_CLK(PS_CLK), // inout wire PS_CLK
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.PS_PORB(PS_PORB) // inout wire PS_PORB
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file zynqps.v when simulating
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// the core, zynqps. When compiling the wrapper file, be sure to
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// reference the Verilog simulation library.
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