105 lines
3.4 KiB
C++
Executable File
105 lines
3.4 KiB
C++
Executable File
/*
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* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
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*
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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* Copyright (c) 2016, Xilinx Inc.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "systemc.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "tlm_utils/tlm_quantumkeeper.h"
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#include "remote-port-tlm.h"
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#include "remote-port-tlm-memory-master.h"
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#include "remote-port-tlm-memory-slave.h"
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#include "remote-port-tlm-wires.h"
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class xilinx_zynq
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: public remoteport_tlm
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{
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private:
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remoteport_tlm_memory_master rp_m_axi_gp0;
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remoteport_tlm_memory_master rp_m_axi_gp1;
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remoteport_tlm_memory_slave rp_s_axi_gp0;
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remoteport_tlm_memory_slave rp_s_axi_gp1;
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remoteport_tlm_memory_slave rp_s_axi_hp0;
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remoteport_tlm_memory_slave rp_s_axi_hp1;
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remoteport_tlm_memory_slave rp_s_axi_hp2;
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remoteport_tlm_memory_slave rp_s_axi_hp3;
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remoteport_tlm_memory_slave rp_s_axi_acp;
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remoteport_tlm_wires rp_wires_in;
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remoteport_tlm_wires rp_wires_out;
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remoteport_tlm_wires rp_irq_out;
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public:
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/*
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* M_AXI_GP 0 - 1.
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* These sockets represent the High speed PS to PL interfaces.
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* These are AXI Slave ports on the PS side and AXI Master ports
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* on the PL side.
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*
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* Used to transfer data from the PS to the PL.
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*/
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tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
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/*
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* S_AXI_GP0 - 1.
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* These sockets represent the High speed IO Coherent PL to PS
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* interfaces.
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*
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* HP0 - 3.
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* These sockets represent the High performance dataflow PL to PS interfaces.
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*
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* ACP
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* Accelerator Coherency Port, used to transfered coherent data to
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* the PS via the Cortex-A9 subsystem.
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*
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* These are AXI Master ports on the PS side and AXI Slave ports
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* on the PL side.
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*
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* Used to transfer data from the PL to the PS.
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*/
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tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
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tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
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tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
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/* PL (fabric) to PS interrupt signals. */
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sc_vector<sc_signal<bool> > pl2ps_irq;
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/* PS to PL Interrupt signals. */
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sc_vector<sc_signal<bool> > ps2pl_irq;
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/* FPGA out resets. */
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sc_vector<sc_signal<bool> > ps2pl_rst;
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xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
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//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
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// Iremoteport_tlm_sync *sync = NULL);
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};
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