132 lines
6.1 KiB
C++
132 lines
6.1 KiB
C++
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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#include "zynqps_sc.h"
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#include "processing_system7_v5_5_tlm.h"
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#include <map>
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#include <string>
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zynqps_sc::zynqps_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
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{
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// configure connectivity manager
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xsc::utils::xsc_sim_manager::addInstance("zynqps", this);
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// initialize module
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xsc::common_cpp::properties model_param_props;
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model_param_props.addLong("C_EN_EMIO_PJTAG", "0");
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model_param_props.addLong("C_EN_EMIO_ENET0", "0");
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model_param_props.addLong("C_EN_EMIO_ENET1", "0");
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model_param_props.addLong("C_EN_EMIO_TRACE", "0");
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model_param_props.addLong("C_INCLUDE_TRACE_BUFFER", "0");
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model_param_props.addLong("C_TRACE_BUFFER_FIFO_SIZE", "128");
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model_param_props.addLong("USE_TRACE_DATA_EDGE_DETECTOR", "0");
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model_param_props.addLong("C_TRACE_PIPELINE_WIDTH", "8");
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model_param_props.addLong("C_TRACE_BUFFER_CLOCK_DELAY", "12");
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model_param_props.addLong("C_EMIO_GPIO_WIDTH", "64");
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model_param_props.addLong("C_INCLUDE_ACP_TRANS_CHECK", "0");
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model_param_props.addLong("C_USE_DEFAULT_ACP_USER_VAL", "0");
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model_param_props.addLong("C_S_AXI_ACP_ARUSER_VAL", "31");
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model_param_props.addLong("C_S_AXI_ACP_AWUSER_VAL", "31");
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model_param_props.addLong("C_M_AXI_GP0_ID_WIDTH", "12");
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model_param_props.addLong("C_M_AXI_GP0_ENABLE_STATIC_REMAP", "0");
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model_param_props.addLong("C_M_AXI_GP1_ID_WIDTH", "12");
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model_param_props.addLong("C_M_AXI_GP1_ENABLE_STATIC_REMAP", "0");
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model_param_props.addLong("C_S_AXI_GP0_ID_WIDTH", "6");
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model_param_props.addLong("C_S_AXI_GP1_ID_WIDTH", "6");
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model_param_props.addLong("C_S_AXI_ACP_ID_WIDTH", "3");
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model_param_props.addLong("C_S_AXI_HP0_ID_WIDTH", "6");
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model_param_props.addLong("C_S_AXI_HP0_DATA_WIDTH", "64");
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model_param_props.addLong("C_S_AXI_HP1_ID_WIDTH", "6");
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model_param_props.addLong("C_S_AXI_HP1_DATA_WIDTH", "64");
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model_param_props.addLong("C_S_AXI_HP2_ID_WIDTH", "6");
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model_param_props.addLong("C_S_AXI_HP2_DATA_WIDTH", "64");
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model_param_props.addLong("C_S_AXI_HP3_ID_WIDTH", "6");
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model_param_props.addLong("C_S_AXI_HP3_DATA_WIDTH", "64");
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model_param_props.addLong("C_M_AXI_GP0_THREAD_ID_WIDTH", "12");
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model_param_props.addLong("C_M_AXI_GP1_THREAD_ID_WIDTH", "12");
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model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "1");
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model_param_props.addLong("C_DQ_WIDTH", "32");
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model_param_props.addLong("C_DQS_WIDTH", "4");
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model_param_props.addLong("C_DM_WIDTH", "4");
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model_param_props.addLong("C_MIO_PRIMITIVE", "54");
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model_param_props.addLong("C_TRACE_INTERNAL_WIDTH", "2");
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model_param_props.addLong("C_USE_AXI_NONSECURE", "0");
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model_param_props.addLong("C_USE_M_AXI_GP0", "0");
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model_param_props.addLong("C_USE_M_AXI_GP1", "0");
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model_param_props.addLong("C_USE_S_AXI_GP0", "0");
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model_param_props.addLong("C_USE_S_AXI_GP1", "0");
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model_param_props.addLong("C_USE_S_AXI_HP0", "0");
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model_param_props.addLong("C_USE_S_AXI_HP1", "0");
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model_param_props.addLong("C_USE_S_AXI_HP2", "0");
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model_param_props.addLong("C_USE_S_AXI_HP3", "0");
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model_param_props.addLong("C_USE_S_AXI_ACP", "0");
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model_param_props.addLong("C_GP0_EN_MODIFIABLE_TXN", "1");
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model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1");
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model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT");
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model_param_props.addString("C_PS7_SI_REV", "PRODUCTION");
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model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE");
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model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE");
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model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE");
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model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE");
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model_param_props.addString("C_PACKAGE_NAME", "clg400");
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model_param_props.addString("COMPONENT_NAME", "zynqps");
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mp_impl = new processing_system7_v5_5_tlm("inst", model_param_props);
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}
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zynqps_sc::~zynqps_sc()
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{
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xsc::utils::xsc_sim_manager::clean();
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delete mp_impl;
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}
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