284 lines
9.4 KiB
C++
284 lines
9.4 KiB
C++
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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#include "zynqps_sc.h"
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#include "zynqps.h"
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#include "processing_system7_v5_5_tlm.h"
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#include <map>
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#include <string>
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#ifdef XILINX_SIMULATOR
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zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
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{
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// initialize pins
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mp_impl->FCLK_CLK0(FCLK_CLK0);
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mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
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mp_impl->MIO(MIO);
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mp_impl->DDR_CAS_n(DDR_CAS_n);
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mp_impl->DDR_CKE(DDR_CKE);
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mp_impl->DDR_Clk_n(DDR_Clk_n);
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mp_impl->DDR_Clk(DDR_Clk);
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mp_impl->DDR_CS_n(DDR_CS_n);
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mp_impl->DDR_DRSTB(DDR_DRSTB);
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mp_impl->DDR_ODT(DDR_ODT);
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mp_impl->DDR_RAS_n(DDR_RAS_n);
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mp_impl->DDR_WEB(DDR_WEB);
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mp_impl->DDR_BankAddr(DDR_BankAddr);
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mp_impl->DDR_Addr(DDR_Addr);
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mp_impl->DDR_VRN(DDR_VRN);
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mp_impl->DDR_VRP(DDR_VRP);
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mp_impl->DDR_DM(DDR_DM);
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mp_impl->DDR_DQ(DDR_DQ);
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mp_impl->DDR_DQS_n(DDR_DQS_n);
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mp_impl->DDR_DQS(DDR_DQS);
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mp_impl->PS_SRSTB(PS_SRSTB);
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mp_impl->PS_CLK(PS_CLK);
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mp_impl->PS_PORB(PS_PORB);
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}
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void zynqps::before_end_of_elaboration()
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{
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}
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#endif // XILINX_SIMULATOR
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#ifdef XM_SYSTEMC
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zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
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{
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// initialize pins
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mp_impl->FCLK_CLK0(FCLK_CLK0);
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mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
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mp_impl->MIO(MIO);
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mp_impl->DDR_CAS_n(DDR_CAS_n);
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mp_impl->DDR_CKE(DDR_CKE);
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mp_impl->DDR_Clk_n(DDR_Clk_n);
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mp_impl->DDR_Clk(DDR_Clk);
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mp_impl->DDR_CS_n(DDR_CS_n);
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mp_impl->DDR_DRSTB(DDR_DRSTB);
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mp_impl->DDR_ODT(DDR_ODT);
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mp_impl->DDR_RAS_n(DDR_RAS_n);
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mp_impl->DDR_WEB(DDR_WEB);
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mp_impl->DDR_BankAddr(DDR_BankAddr);
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mp_impl->DDR_Addr(DDR_Addr);
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mp_impl->DDR_VRN(DDR_VRN);
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mp_impl->DDR_VRP(DDR_VRP);
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mp_impl->DDR_DM(DDR_DM);
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mp_impl->DDR_DQ(DDR_DQ);
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mp_impl->DDR_DQS_n(DDR_DQS_n);
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mp_impl->DDR_DQS(DDR_DQS);
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mp_impl->PS_SRSTB(PS_SRSTB);
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mp_impl->PS_CLK(PS_CLK);
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mp_impl->PS_PORB(PS_PORB);
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}
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void zynqps::before_end_of_elaboration()
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{
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}
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#endif // XM_SYSTEMC
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#ifdef RIVIERA
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zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
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{
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// initialize pins
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mp_impl->FCLK_CLK0(FCLK_CLK0);
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mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
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mp_impl->MIO(MIO);
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mp_impl->DDR_CAS_n(DDR_CAS_n);
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mp_impl->DDR_CKE(DDR_CKE);
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mp_impl->DDR_Clk_n(DDR_Clk_n);
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mp_impl->DDR_Clk(DDR_Clk);
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mp_impl->DDR_CS_n(DDR_CS_n);
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mp_impl->DDR_DRSTB(DDR_DRSTB);
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mp_impl->DDR_ODT(DDR_ODT);
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mp_impl->DDR_RAS_n(DDR_RAS_n);
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mp_impl->DDR_WEB(DDR_WEB);
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mp_impl->DDR_BankAddr(DDR_BankAddr);
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mp_impl->DDR_Addr(DDR_Addr);
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mp_impl->DDR_VRN(DDR_VRN);
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mp_impl->DDR_VRP(DDR_VRP);
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mp_impl->DDR_DM(DDR_DM);
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mp_impl->DDR_DQ(DDR_DQ);
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mp_impl->DDR_DQS_n(DDR_DQS_n);
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mp_impl->DDR_DQS(DDR_DQS);
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mp_impl->PS_SRSTB(PS_SRSTB);
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mp_impl->PS_CLK(PS_CLK);
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mp_impl->PS_PORB(PS_PORB);
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}
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void zynqps::before_end_of_elaboration()
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{
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}
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#endif // RIVIERA
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#ifdef VCSSYSTEMC
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zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
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{
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// initialize pins
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mp_impl->FCLK_CLK0(FCLK_CLK0);
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mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
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mp_impl->MIO(MIO);
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mp_impl->DDR_CAS_n(DDR_CAS_n);
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mp_impl->DDR_CKE(DDR_CKE);
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mp_impl->DDR_Clk_n(DDR_Clk_n);
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mp_impl->DDR_Clk(DDR_Clk);
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mp_impl->DDR_CS_n(DDR_CS_n);
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mp_impl->DDR_DRSTB(DDR_DRSTB);
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mp_impl->DDR_ODT(DDR_ODT);
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mp_impl->DDR_RAS_n(DDR_RAS_n);
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mp_impl->DDR_WEB(DDR_WEB);
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mp_impl->DDR_BankAddr(DDR_BankAddr);
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mp_impl->DDR_Addr(DDR_Addr);
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mp_impl->DDR_VRN(DDR_VRN);
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mp_impl->DDR_VRP(DDR_VRP);
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mp_impl->DDR_DM(DDR_DM);
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mp_impl->DDR_DQ(DDR_DQ);
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mp_impl->DDR_DQS_n(DDR_DQS_n);
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mp_impl->DDR_DQS(DDR_DQS);
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mp_impl->PS_SRSTB(PS_SRSTB);
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mp_impl->PS_CLK(PS_CLK);
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mp_impl->PS_PORB(PS_PORB);
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// Instantiate Socket Stubs
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}
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void zynqps::before_end_of_elaboration()
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{
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}
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#endif // VCSSYSTEMC
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#ifdef MTI_SYSTEMC
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zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
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{
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// initialize pins
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mp_impl->FCLK_CLK0(FCLK_CLK0);
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mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
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mp_impl->MIO(MIO);
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mp_impl->DDR_CAS_n(DDR_CAS_n);
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mp_impl->DDR_CKE(DDR_CKE);
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mp_impl->DDR_Clk_n(DDR_Clk_n);
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mp_impl->DDR_Clk(DDR_Clk);
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mp_impl->DDR_CS_n(DDR_CS_n);
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mp_impl->DDR_DRSTB(DDR_DRSTB);
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mp_impl->DDR_ODT(DDR_ODT);
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mp_impl->DDR_RAS_n(DDR_RAS_n);
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mp_impl->DDR_WEB(DDR_WEB);
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mp_impl->DDR_BankAddr(DDR_BankAddr);
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mp_impl->DDR_Addr(DDR_Addr);
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mp_impl->DDR_VRN(DDR_VRN);
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mp_impl->DDR_VRP(DDR_VRP);
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mp_impl->DDR_DM(DDR_DM);
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mp_impl->DDR_DQ(DDR_DQ);
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mp_impl->DDR_DQS_n(DDR_DQS_n);
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mp_impl->DDR_DQS(DDR_DQS);
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mp_impl->PS_SRSTB(PS_SRSTB);
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mp_impl->PS_CLK(PS_CLK);
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mp_impl->PS_PORB(PS_PORB);
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// Instantiate Socket Stubs
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}
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void zynqps::before_end_of_elaboration()
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{
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}
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#endif // MTI_SYSTEMC
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zynqps::~zynqps()
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{
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}
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#ifdef MTI_SYSTEMC
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SC_MODULE_EXPORT(zynqps);
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#endif
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#ifdef XM_SYSTEMC
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XMSC_MODULE_EXPORT(zynqps);
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#endif
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#ifdef RIVIERA
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SC_MODULE_EXPORT(zynqps);
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SC_REGISTER_BV(54);
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#endif
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