53 lines
2.2 KiB
VHDL
53 lines
2.2 KiB
VHDL
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
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-- Date : Mon Sep 5 15:07:17 2022
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-- Host : NotSoStraightDPC running 64-bit Arch Linux
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-- Command : write_vhdl -force -mode synth_stub
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-- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl
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-- Design : zynqps
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z010clg400-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity zynqps is
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Port (
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FCLK_CLK0 : out STD_LOGIC;
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FCLK_RESET0_N : out STD_LOGIC;
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MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
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DDR_CAS_n : inout STD_LOGIC;
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DDR_CKE : inout STD_LOGIC;
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DDR_Clk_n : inout STD_LOGIC;
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DDR_Clk : inout STD_LOGIC;
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DDR_CS_n : inout STD_LOGIC;
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DDR_DRSTB : inout STD_LOGIC;
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DDR_ODT : inout STD_LOGIC;
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DDR_RAS_n : inout STD_LOGIC;
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DDR_WEB : inout STD_LOGIC;
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DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
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DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
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DDR_VRN : inout STD_LOGIC;
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DDR_VRP : inout STD_LOGIC;
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DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
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DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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PS_SRSTB : inout STD_LOGIC;
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PS_CLK : inout STD_LOGIC;
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PS_PORB : inout STD_LOGIC
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);
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end zynqps;
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architecture stub of zynqps is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
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attribute x_core_info : string;
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attribute x_core_info of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2021.2";
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begin
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end;
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