94 lines
3.8 KiB
VHDL
94 lines
3.8 KiB
VHDL
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-- DO NOT MODIFY THIS FILE.
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-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
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-- IP Revision: 13
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-- The following code must appear in the VHDL architecture header.
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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COMPONENT rst_gen
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PORT (
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slowest_sync_clk : IN STD_LOGIC;
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ext_reset_in : IN STD_LOGIC;
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aux_reset_in : IN STD_LOGIC;
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mb_debug_sys_rst : IN STD_LOGIC;
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dcm_locked : IN STD_LOGIC;
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mb_reset : OUT STD_LOGIC;
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bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
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);
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END COMPONENT;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : rst_gen
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PORT MAP (
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slowest_sync_clk => slowest_sync_clk,
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ext_reset_in => ext_reset_in,
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aux_reset_in => aux_reset_in,
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mb_debug_sys_rst => mb_debug_sys_rst,
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dcm_locked => dcm_locked,
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mb_reset => mb_reset,
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bus_struct_reset => bus_struct_reset,
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peripheral_reset => peripheral_reset,
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interconnect_aresetn => interconnect_aresetn,
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peripheral_aresetn => peripheral_aresetn
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);
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-- INST_TAG_END ------ End INSTANTIATION Template ---------
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-- You must compile the wrapper file rst_gen.vhd when simulating
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-- the core, rst_gen. When compiling the wrapper file, be sure to
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-- reference the VHDL simulation library.
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