Joppe Blondel 96a406b2eb Full bit and timing log generation ...

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

2022-09-05 12:38:21 +02:00

..

CON

Added impl

2022-09-04 19:48:46 +02:00

RTL

Added impl

2022-09-04 19:48:46 +02:00

SIM

Added impl

2022-09-04 19:48:46 +02:00

.gitignore

Added impl

2022-09-04 19:48:46 +02:00

project.cfg

Full bit and timing log generation

2022-09-05 12:38:21 +02:00