202 lines
5.8 KiB
INI
202 lines
5.8 KiB
INI
[project]
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name = zynq7000_project
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version = 0.1
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out_dir = OUT
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build_dir = BUILD
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[server]
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hostname = localhost
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port = 2020
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privkey = /home/joppe/.ssh/id_rsa
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pubkey = /home/joppe/.ssh/id_rsa.pub
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# ======================================
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# BASIC FPGA WORKFLOW
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# ======================================
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# ######################################
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# ISE IP block generation
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[target.ip]
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toolchain = VIVADO_IP
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# Toolchain settings
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family = zynq
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device = xc7z010
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package = clg400
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speedgrade = -2
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# Fileset
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files_tcl = IP/zynqps.tcl IP/rst_gen.tcl
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# Note: IP file names must be the same as the component name in the tcl file!
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# ######################################
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# ######################################
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# Basic synthesis
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[target.synth]
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toolchain = VIVADO
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# Toolchain settings
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family = zynq
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device = xc7z010
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package = clg400
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speedgrade = -2
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toplevel = toplevel
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# Created netlist toplevel
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netlist_top = toplevel.heartbeat_i heartbeat
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# toplevel and name to give to exported netlist
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synth_opts = -flatten_hierarchy none -keep_equivalent_registers
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#opt_opts =
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#place_opts =
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#route_opts =
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# Fileset
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files_vhdl = RTL/heartbeat.vhd RTL/toplevel.vhd
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#files_verilog =
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#files_sysverilog =
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files_con = CON/toplevel.xdc
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files_xci = OUT/ip/rst_gen/rst_gen.xci OUT/ip/zynqps/zynqps.xci
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# ######################################
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# ######################################
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# Behavioural simulation
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[target.sim]
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toolchain = xsim
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# Toolchain settings
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toplevel = tb_heartbeat
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vcdlevels = 20
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runtime = all
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#xelab_opts =
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# Fileset
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files_vhdl = RTL/heartbeat.vhd
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SIM/tb_heartbeat.vhd
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#files_verilog =
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#files_sysverilog =
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#files_xci =
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# ######################################
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# ######################################
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# Post synthesis simulation (synth must have ran first)
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[target.psim]
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toolchain = xsim
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# Toolchain settings
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toplevel = tb_heartbeat
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vcdlevels = 20
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runtime = all
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xelab_opts = -maxdelay -transport_int_delays -L simprims_ver
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# Fileset
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files_vhdl = SIM/tb_heartbeat.vhd
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files_verilog = OUT/synth/impl_netlist.v
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#files_sysverilog =
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#files_xci =
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files_other = OUT/synth/impl_netlist.sdf
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# ######################################
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# ======================================
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# PS/PL workflow
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# ======================================
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# ######################################
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# Firmware compilation
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[target.firmware]
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toolchain = make
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# Toolchain settings
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output_files = build/app.elf DISASS
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buildroot = SW
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# Fileset
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files_makefile = SW/Makefile
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files_other = SW/linker.ld
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SW/src/boot.S
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SW/src/main.c
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SW/src/printf.c
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SW/src/printf.h
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SW/src/uart.c
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SW/src/uart.h
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SW/src/xil_io.h
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SW/src/zynq.h
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OUT/ip/zynqps/ps7_init.c
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OUT/ip/zynqps/ps7_init.h
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# ######################################
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# ######################################
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# Firmware simulation
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[target.firmsim]
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toolchain = qemu
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# Toolchain settings
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arch = arm
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machine = xilinx-zynq-a9
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ram = 256M
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extra_opts = -serial /dev/null -serial mon:stdio
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# Fileset
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files_executable = OUT/firmware/app.elf
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# ######################################
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# ######################################
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# Device tree compilation
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[target.devtree]
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toolchain = make
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# Toolchain settings
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output_files = system.dtb system.dts
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buildroot = SW/devicetree
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# Fileset
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files_makefile = SW/devicetree/Makefile
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files_other = SW/devicetree/pcw.dtsi
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SW/devicetree/pl.dtsi
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SW/devicetree/skeleton.dtsi
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SW/devicetree/system-top.dts
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SW/devicetree/zynq-7000.dtsi
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SW/devicetree/zynq-pl-remoteport.dtsi
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SW/devicetree/include/dt-bindings/clock/xlnx-versal-clk.h
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SW/devicetree/include/dt-bindings/power/xlnx-versal-power.h
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SW/devicetree/include/dt-bindings/reset/xlnx-versal-resets.h
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# ######################################
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# ######################################
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# Hardware-firmware cosimulation PS part
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[target.cosim_ps]
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toolchain = qemu
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# Toolchain settings
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arch = xilinxarm
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machine = arm-generic-fdt-7series
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ram = 256M
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extra_opts = -serial /dev/null -serial mon:stdio -dtb ../OUT/devtree/system.dtb \
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-machine-path /tmp \
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-icount 1 -sync-quantum 100000 \
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-device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4
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# Fileset
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files_executable = OUT/firmware/app.elf
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files_other = OUT/devtree/system.dtb
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# ######################################
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# ######################################
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# Hardware-firmware cosimulation PL part
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# Note: currently not using xsim since compilation with xilinx
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# provided tools are horrible on linux
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[target.cosim_pl]
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toolchain = questa
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# Toolchain settings
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toplevel = tb_cosim
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vcdlevels = 20
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runtime = all
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# Fileset
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files_vhdl = RTL/heartbeat.vhd
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# files_verilog =
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files_sysverilog = SIM/tb_cosim.sv
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files_c = SIM/c/remote-port-proto.c SIM/c/cosim.c
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files_other = SIM/c/remote-port-proto.h
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# ###################################### |