23 lines
555 B
VHDL
23 lines
555 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity toplevel is
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port (
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ACLK : in std_logic;
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LED : out std_logic_vector(7 downto 0);
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SW : in std_logic_vector(3 downto 0)
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);
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end toplevel;
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architecture structural of toplevel is
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signal ARESETN : std_logic;
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begin
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ARESETN <= SW(3);
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process(ACLK, ARESETN)
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begin
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if ARESETN='0' then
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LED <= "11111111";
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elsif rising_edge(ACLK) then
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LED <= SW & SW;
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end if;
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end process;
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end architecture; |