91 lines
2.3 KiB
INI
91 lines
2.3 KiB
INI
[project]
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name = spartan6_project
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version = 0.1
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out_dir = OUT
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build_dir = BUILD
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[server]
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hostname = localhost
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port = 2020
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privkey = /home/joppe/.ssh/id_rsa
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pubkey = /home/joppe/.ssh/id_rsa.pub
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# ######################################
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# ISE IP block generation
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[target.ip]
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toolchain = ISE_IP
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# Toolchain settings
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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#coregen_opts =
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# Fileset
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files_xco = IP/blk_mem.xco
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# Note: IP file names must be the same as the component name in the xco file!
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# ######################################
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# ######################################
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# Basic synthesis
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[target.synth]
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toolchain = ISE
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# Toolchain settings
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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toplevel = toplevel
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#xst_opts =
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#ngdbuild_opts =
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#map_opts =
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#par_opts =
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#netgen_opts =
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#bitgen_opts =
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#trce_opts =
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# Fileset
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files_vhdl = RTL/toplevel.vhd
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#files_verilog =
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files_con = CON/toplevel.ucf
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# ######################################
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# ######################################
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# Behavioural simulation
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[target.sim]
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toolchain = isim
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# Toolchain settings
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toplevel = tb_toplevel
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vcdlevels = 20
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runtime = all
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#fuse_opts =
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#isim_opts =
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# Fileset
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files_vhdl = RTL/toplevel.vhd
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SIM/tb_toplevel.vhd
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#files_verilog =
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# ######################################
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# ######################################
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# Post synthesis simulation (synth must have ran first)
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[target.psim]
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toolchain = isim
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# Toolchain settings
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toplevel = tb_toplevel
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vcdlevels = 20
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runtime = all
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fuse_opts = --maxdelay work.glbl
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isim_opts = -sdfmax /tb_toplevel/c_toplevel=~D~/OUT/synth/synth.sdf
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# ~D~ is replaced with the top directory of the project
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# Fileset
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files_vhdl = SIM/tb_toplevel.vhd
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files_verilog = OUT/synth/synth.v
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files_other = OUT/synth/synth.sdf
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# ###################################### |