48 lines
1.1 KiB
VHDL
48 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_counter is
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end entity;
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architecture behav of tb_counter is
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component counter is
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generic (
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formal : boolean := false;
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width : integer := 16;
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mxcnt : integer := 256
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);
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port (
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ACLK : in std_logic;
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ARESETN : in std_logic;
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cnt : out std_logic_vector(width-1 downto 0)
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);
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end component;
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signal ACLK, ARESETN : std_logic := '0';
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signal cnt : std_logic_vector(15 downto 0);
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begin
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ACLK <= not ACLK after 10 ns;
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ARESETN <= '1' after 50 ns;
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process
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begin
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wait for 2 us;
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report "END OF SIMULATION" severity failure;
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end process;
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c_counter : component counter
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generic map(
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formal => false,
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width => cnt'length,
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mxcnt => 5
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) port map (
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ACLK => ACLK,
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ARESETN => ARESETN,
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cnt => cnt
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);
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end architecture; |