23 lines
391 B
Verilog
23 lines
391 B
Verilog
module led_blink
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(
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input clk_i,
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input reset_n_i,
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output led_o
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);
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reg [23:0] counter;
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reg polarity;
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always@(posedge clk_i) begin
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if (!reset_n_i)
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counter <= 24'h00000;
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else
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counter <= counter + 1'b1;
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if (counter == 24'hFFFFF)
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polarity <= ~polarity;
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end
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assign led_o = polarity;
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endmodule |