xilinx.com customized_ip zynqps 1.0 GMII_ETHERNET_0 TX_EN ENET0_GMII_TX_EN TX_ER ENET0_GMII_TX_ER TXD ENET0_GMII_TXD COL ENET0_GMII_COL CRS ENET0_GMII_CRS RX_CLK ENET0_GMII_RX_CLK RX_DV ENET0_GMII_RX_DV RX_ER ENET0_GMII_RX_ER TX_CLK ENET0_GMII_TX_CLK RXD ENET0_GMII_RXD false MDIO_ETHERNET_0 MDC ENET0_MDIO_MDC MDIO_O ENET0_MDIO_O MDIO_T ENET0_MDIO_T MDIO_I ENET0_MDIO_I CAN_DEBUG false none false PTP_ETHERNET_0 DELAY_REQ_RX ENET0_PTP_DELAY_REQ_RX DELAY_REQ_TX ENET0_PTP_DELAY_REQ_TX PDELAY_REQ_RX ENET0_PTP_PDELAY_REQ_RX PDELAY_REQ_TX ENET0_PTP_PDELAY_REQ_TX PDELAY_RESP_RX ENET0_PTP_PDELAY_RESP_RX PDELAY_RESP_TX ENET0_PTP_PDELAY_RESP_TX SYNC_FRAME_RX ENET0_PTP_SYNC_FRAME_RX SYNC_FRAME_TX ENET0_PTP_SYNC_FRAME_TX SOF_RX ENET0_SOF_RX SOF_TX ENET0_SOF_TX false ENET0_EXT_INTIN INTERRUPT ENET0_EXT_INTIN SENSITIVITY LEVEL_HIGH none PortWidth 1 none false GMII_ETHERNET_1 TX_EN ENET1_GMII_TX_EN TX_ER ENET1_GMII_TX_ER TXD ENET1_GMII_TXD COL ENET1_GMII_COL CRS ENET1_GMII_CRS RX_CLK ENET1_GMII_RX_CLK RX_DV ENET1_GMII_RX_DV RX_ER ENET1_GMII_RX_ER TX_CLK ENET1_GMII_TX_CLK RXD ENET1_GMII_RXD false MDIO_ETHERNET_1 MDC ENET1_MDIO_MDC MDIO_O ENET1_MDIO_O MDIO_T ENET1_MDIO_T MDIO_I ENET1_MDIO_I CAN_DEBUG false none false PTP_ETHERNET_1 DELAY_REQ_RX ENET1_PTP_DELAY_REQ_RX DELAY_REQ_TX ENET1_PTP_DELAY_REQ_TX PDELAY_REQ_RX ENET1_PTP_PDELAY_REQ_RX PDELAY_REQ_TX ENET1_PTP_PDELAY_REQ_TX PDELAY_RESP_RX ENET1_PTP_PDELAY_RESP_RX PDELAY_RESP_TX ENET1_PTP_PDELAY_RESP_TX SYNC_FRAME_RX ENET1_PTP_SYNC_FRAME_RX SYNC_FRAME_TX ENET1_PTP_SYNC_FRAME_TX SOF_RX ENET1_SOF_RX SOF_TX ENET1_SOF_TX false ENET1_EXT_INTIN INTERRUPT ENET1_EXT_INTIN SENSITIVITY LEVEL_HIGH none PortWidth 1 none false GPIO_0 TRI_I GPIO_I TRI_O GPIO_O TRI_T GPIO_T false DDR CAS_N DDR_CAS_n CKE DDR_CKE CK_N DDR_Clk_n CK_P DDR_Clk CS_N DDR_CS_n RESET_N DDR_DRSTB ODT DDR_ODT RAS_N DDR_RAS_n WE_N DDR_WEB BA DDR_BankAddr ADDR DDR_Addr DM DDR_DM DQ DDR_DQ DQS_N DDR_DQS_n DQS_P DDR_DQS CAN_DEBUG false none TIMEPERIOD_PS 1250 none MEMORY_TYPE COMPONENTS none MEMORY_PART none DATA_WIDTH 8 none CS_ENABLED true none DATA_MASK_ENABLED true none SLOT Single none CUSTOM_PARTS none MEM_ADDR_MAP ROW_COLUMN_BANK none BURST_LENGTH 8 none AXI_ARBITRATION_SCHEME TDM none CAS_LATENCY 11 none CAS_WRITE_LATENCY 11 none true FIXED_IO MIO MIO DDR_VRN DDR_VRN DDR_VRP DDR_VRP PS_SRSTB PS_SRSTB PS_CLK PS_CLK PS_PORB PS_PORB CAN_DEBUG false none UART_0 DTRn UART0_DTRN RTSn UART0_RTSN TxD UART0_TX CTSn UART0_CTSN DCDn UART0_DCDN DSRn UART0_DSRN RI UART0_RIN RxD UART0_RX false UART_1 DTRn UART1_DTRN RTSn UART1_RTSN TxD UART1_TX CTSn UART1_CTSN DCDn UART1_DCDN DSRn UART1_DSRN RI UART1_RIN RxD UART1_RX false IIC_0 SDA_I I2C0_SDA_I SDA_O I2C0_SDA_O SDA_T I2C0_SDA_T SCL_I I2C0_SCL_I SCL_O I2C0_SCL_O SCL_T I2C0_SCL_T false IIC_1 SDA_I I2C1_SDA_I SDA_O I2C1_SDA_O SDA_T I2C1_SDA_T SCL_I I2C1_SCL_I SCL_O I2C1_SCL_O SCL_T I2C1_SCL_T false SPI_0 SCK_I SPI0_SCLK_I SCK_O SPI0_SCLK_O SCK_T SPI0_SCLK_T IO0_I SPI0_MOSI_I IO0_O SPI0_MOSI_O IO0_T SPI0_MOSI_T IO1_I SPI0_MISO_I IO1_O SPI0_MISO_O IO1_T SPI0_MISO_T SS_I SPI0_SS_I SS_O SPI0_SS_O SS1_O SPI0_SS1_O SS2_O SPI0_SS2_O SS_T SPI0_SS_T false SPI_1 SCK_I SPI1_SCLK_I SCK_O SPI1_SCLK_O SCK_T SPI1_SCLK_T IO0_I SPI1_MOSI_I IO0_O SPI1_MOSI_O IO0_T SPI1_MOSI_T IO1_I SPI1_MISO_I IO1_O SPI1_MISO_O IO1_T SPI1_MISO_T SS_I SPI1_SS_I SS_O SPI1_SS_O SS1_O SPI1_SS1_O SS2_O SPI1_SS2_O SS_T SPI1_SS_T false CAN_0 TX CAN0_PHY_TX RX CAN0_PHY_RX false CAN_1 TX CAN1_PHY_TX RX CAN1_PHY_RX false PJTAG TCK PJTAG_TCK TMS PJTAG_TMS TDI PJTAG_TDI TDO PJTAG_TDO false SDIO_0 CLK SDIO0_CLK CLK_FB SDIO0_CLK_FB CMD_O SDIO0_CMD_O CMD_I SDIO0_CMD_I CMD_T SDIO0_CMD_T DATA_I SDIO0_DATA_I DATA_O SDIO0_DATA_O DATA_T SDIO0_DATA_T LED SDIO0_LED CDN SDIO0_CDN WP SDIO0_WP BUSPOW SDIO0_BUSPOW BUSVOLT SDIO0_BUSVOLT false SDIO_1 CLK SDIO1_CLK CLK_FB SDIO1_CLK_FB CMD_O SDIO1_CMD_O CMD_I SDIO1_CMD_I CMD_T SDIO1_CMD_T DATA_I SDIO1_DATA_I DATA_O SDIO1_DATA_O DATA_T SDIO1_DATA_T LED SDIO1_LED CDN SDIO1_CDN WP SDIO1_WP BUSPOW SDIO1_BUSPOW BUSVOLT SDIO1_BUSVOLT false TRACE_0 CLK_O TRACE_CLK_OUT CLK_I TRACE_CLK CTL TRACE_CTL DATA TRACE_DATA false USBIND_0 PORT_INDCTL USB0_PORT_INDCTL VBUS_PWRSELECT USB0_VBUS_PWRSELECT VBUS_PWRFAULT USB0_VBUS_PWRFAULT false USBIND_1 PORT_INDCTL USB1_PORT_INDCTL VBUS_PWRSELECT USB1_VBUS_PWRSELECT VBUS_PWRFAULT USB1_VBUS_PWRFAULT false S_AXI_HP0_FIFO_CTRL RCOUNT S_AXI_HP0_RCOUNT WCOUNT S_AXI_HP0_WCOUNT RACOUNT S_AXI_HP0_RACOUNT WACOUNT S_AXI_HP0_WACOUNT RDISSUECAPEN S_AXI_HP0_RDISSUECAP1_EN WRISSUECAPEN S_AXI_HP0_WRISSUECAP1_EN false S_AXI_HP1_FIFO_CTRL RCOUNT S_AXI_HP1_RCOUNT WCOUNT S_AXI_HP1_WCOUNT RACOUNT S_AXI_HP1_RACOUNT WACOUNT S_AXI_HP1_WACOUNT RDISSUECAPEN S_AXI_HP1_RDISSUECAP1_EN WRISSUECAPEN S_AXI_HP1_WRISSUECAP1_EN false S_AXI_HP2_FIFO_CTRL RCOUNT S_AXI_HP2_RCOUNT WCOUNT S_AXI_HP2_WCOUNT RACOUNT S_AXI_HP2_RACOUNT WACOUNT S_AXI_HP2_WACOUNT RDISSUECAPEN S_AXI_HP2_RDISSUECAP1_EN WRISSUECAPEN S_AXI_HP2_WRISSUECAP1_EN false S_AXI_HP3_FIFO_CTRL RCOUNT S_AXI_HP3_RCOUNT WCOUNT S_AXI_HP3_WCOUNT RACOUNT S_AXI_HP3_RACOUNT WACOUNT S_AXI_HP3_WACOUNT RDISSUECAPEN S_AXI_HP3_RDISSUECAP1_EN WRISSUECAPEN S_AXI_HP3_WRISSUECAP1_EN false DMA0_REQ TREADY DMA0_DRREADY TLAST DMA0_DRLAST TVALID DMA0_DRVALID TUSER DMA0_DRTYPE TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA0_ACK TUSER DMA0_DATYPE TVALID DMA0_DAVALID TREADY DMA0_DAREADY TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA1_REQ TREADY DMA1_DRREADY TLAST DMA1_DRLAST TVALID DMA1_DRVALID TUSER DMA1_DRTYPE TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA1_ACK TUSER DMA1_DATYPE TVALID DMA1_DAVALID TREADY DMA1_DAREADY TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA2_REQ TREADY DMA2_DRREADY TLAST DMA2_DRLAST TVALID DMA2_DRVALID TUSER DMA2_DRTYPE TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA2_ACK TUSER DMA2_DATYPE TVALID DMA2_DAVALID TREADY DMA2_DAREADY TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA3_REQ TREADY DMA3_DRREADY TLAST DMA3_DRLAST TVALID DMA3_DRVALID TUSER DMA3_DRTYPE TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false DMA3_ACK TUSER DMA3_DATYPE TVALID DMA3_DAVALID TREADY DMA3_DAREADY TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false FTM_TRACE_DATA TDATA FTMD_TRACEIN_DATA TVALID FTMD_TRACEIN_VALID TID FTMD_TRACEIN_ATID TDATA_NUM_BYTES 0 simulation.tlm TDEST_WIDTH 0 simulation.tlm TID_WIDTH 0 simulation.tlm TUSER_WIDTH 0 simulation.tlm HAS_TREADY 0 simulation.tlm HAS_TSTRB 0 simulation.tlm HAS_TKEEP 0 simulation.tlm HAS_TLAST 0 simulation.tlm FREQ_HZ 100000000 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm LAYERED_METADATA undef simulation.tlm INSERT_VIP 0 simulation.rtl false PROC_EVENT EVENTO EVENT_EVENTO STANDBYWFE EVENT_STANDBYWFE STANDBYWFI EVENT_STANDBYWFI EVENTI EVENT_EVENTI false M_AXI_GP0 0x40000000 ARVALID M_AXI_GP0_ARVALID AWVALID M_AXI_GP0_AWVALID BREADY M_AXI_GP0_BREADY RREADY M_AXI_GP0_RREADY WLAST M_AXI_GP0_WLAST WVALID M_AXI_GP0_WVALID ARID M_AXI_GP0_ARID AWID M_AXI_GP0_AWID WID M_AXI_GP0_WID ARBURST M_AXI_GP0_ARBURST ARLOCK M_AXI_GP0_ARLOCK ARSIZE M_AXI_GP0_ARSIZE AWBURST M_AXI_GP0_AWBURST AWLOCK M_AXI_GP0_AWLOCK AWSIZE M_AXI_GP0_AWSIZE ARPROT M_AXI_GP0_ARPROT AWPROT M_AXI_GP0_AWPROT ARADDR M_AXI_GP0_ARADDR AWADDR M_AXI_GP0_AWADDR WDATA M_AXI_GP0_WDATA ARCACHE M_AXI_GP0_ARCACHE ARLEN M_AXI_GP0_ARLEN ARQOS M_AXI_GP0_ARQOS AWCACHE M_AXI_GP0_AWCACHE AWLEN M_AXI_GP0_AWLEN AWQOS M_AXI_GP0_AWQOS WSTRB M_AXI_GP0_WSTRB ARREADY M_AXI_GP0_ARREADY AWREADY M_AXI_GP0_AWREADY BVALID M_AXI_GP0_BVALID RLAST M_AXI_GP0_RLAST RVALID M_AXI_GP0_RVALID WREADY M_AXI_GP0_WREADY BID M_AXI_GP0_BID RID M_AXI_GP0_RID BRESP M_AXI_GP0_BRESP RRESP M_AXI_GP0_RRESP RDATA M_AXI_GP0_RDATA SUPPORTS_NARROW_BURST 0 false NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false M_AXI_GP1 0x80000000 ARVALID M_AXI_GP1_ARVALID AWVALID M_AXI_GP1_AWVALID BREADY M_AXI_GP1_BREADY RREADY M_AXI_GP1_RREADY WLAST M_AXI_GP1_WLAST WVALID M_AXI_GP1_WVALID ARID M_AXI_GP1_ARID AWID M_AXI_GP1_AWID WID M_AXI_GP1_WID ARBURST M_AXI_GP1_ARBURST ARLOCK M_AXI_GP1_ARLOCK ARSIZE M_AXI_GP1_ARSIZE AWBURST M_AXI_GP1_AWBURST AWLOCK M_AXI_GP1_AWLOCK AWSIZE M_AXI_GP1_AWSIZE ARPROT M_AXI_GP1_ARPROT AWPROT M_AXI_GP1_AWPROT ARADDR M_AXI_GP1_ARADDR AWADDR M_AXI_GP1_AWADDR WDATA M_AXI_GP1_WDATA ARCACHE M_AXI_GP1_ARCACHE ARLEN M_AXI_GP1_ARLEN ARQOS M_AXI_GP1_ARQOS AWCACHE M_AXI_GP1_AWCACHE AWLEN M_AXI_GP1_AWLEN AWQOS M_AXI_GP1_AWQOS WSTRB M_AXI_GP1_WSTRB ARREADY M_AXI_GP1_ARREADY AWREADY M_AXI_GP1_AWREADY BVALID M_AXI_GP1_BVALID RLAST M_AXI_GP1_RLAST RVALID M_AXI_GP1_RVALID WREADY M_AXI_GP1_WREADY BID M_AXI_GP1_BID RID M_AXI_GP1_RID BRESP M_AXI_GP1_BRESP RRESP M_AXI_GP1_RRESP RDATA M_AXI_GP1_RDATA NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 SUPPORTS_NARROW_BURST 0 false DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_ACP ARREADY S_AXI_ACP_ARREADY AWREADY S_AXI_ACP_AWREADY BVALID S_AXI_ACP_BVALID RLAST S_AXI_ACP_RLAST RVALID S_AXI_ACP_RVALID WREADY S_AXI_ACP_WREADY BRESP S_AXI_ACP_BRESP RRESP S_AXI_ACP_RRESP BID S_AXI_ACP_BID RID S_AXI_ACP_RID RDATA S_AXI_ACP_RDATA ARVALID S_AXI_ACP_ARVALID AWVALID S_AXI_ACP_AWVALID BREADY S_AXI_ACP_BREADY RREADY S_AXI_ACP_RREADY WLAST S_AXI_ACP_WLAST WVALID S_AXI_ACP_WVALID ARID S_AXI_ACP_ARID ARPROT S_AXI_ACP_ARPROT AWID S_AXI_ACP_AWID AWPROT S_AXI_ACP_AWPROT WID S_AXI_ACP_WID ARADDR S_AXI_ACP_ARADDR AWADDR S_AXI_ACP_AWADDR ARCACHE S_AXI_ACP_ARCACHE ARLEN S_AXI_ACP_ARLEN ARQOS S_AXI_ACP_ARQOS AWCACHE S_AXI_ACP_AWCACHE AWLEN S_AXI_ACP_AWLEN AWQOS S_AXI_ACP_AWQOS ARBURST S_AXI_ACP_ARBURST ARLOCK S_AXI_ACP_ARLOCK ARSIZE S_AXI_ACP_ARSIZE AWBURST S_AXI_ACP_AWBURST AWLOCK S_AXI_ACP_AWLOCK AWSIZE S_AXI_ACP_AWSIZE ARUSER S_AXI_ACP_ARUSER AWUSER S_AXI_ACP_AWUSER WDATA S_AXI_ACP_WDATA WSTRB S_AXI_ACP_WSTRB NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_GP0 ARREADY S_AXI_GP0_ARREADY AWREADY S_AXI_GP0_AWREADY BVALID S_AXI_GP0_BVALID RLAST S_AXI_GP0_RLAST RVALID S_AXI_GP0_RVALID WREADY S_AXI_GP0_WREADY BRESP S_AXI_GP0_BRESP RRESP S_AXI_GP0_RRESP RDATA S_AXI_GP0_RDATA BID S_AXI_GP0_BID RID S_AXI_GP0_RID ARVALID S_AXI_GP0_ARVALID AWVALID S_AXI_GP0_AWVALID BREADY S_AXI_GP0_BREADY RREADY S_AXI_GP0_RREADY WLAST S_AXI_GP0_WLAST WVALID S_AXI_GP0_WVALID ARBURST S_AXI_GP0_ARBURST ARLOCK S_AXI_GP0_ARLOCK ARSIZE S_AXI_GP0_ARSIZE AWBURST S_AXI_GP0_AWBURST AWLOCK S_AXI_GP0_AWLOCK AWSIZE S_AXI_GP0_AWSIZE ARPROT S_AXI_GP0_ARPROT AWPROT S_AXI_GP0_AWPROT ARADDR S_AXI_GP0_ARADDR AWADDR S_AXI_GP0_AWADDR WDATA S_AXI_GP0_WDATA ARCACHE S_AXI_GP0_ARCACHE ARLEN S_AXI_GP0_ARLEN ARQOS S_AXI_GP0_ARQOS AWCACHE S_AXI_GP0_AWCACHE AWLEN S_AXI_GP0_AWLEN AWQOS S_AXI_GP0_AWQOS WSTRB S_AXI_GP0_WSTRB ARID S_AXI_GP0_ARID AWID S_AXI_GP0_AWID WID S_AXI_GP0_WID NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_GP1 ARREADY S_AXI_GP1_ARREADY AWREADY S_AXI_GP1_AWREADY BVALID S_AXI_GP1_BVALID RLAST S_AXI_GP1_RLAST RVALID S_AXI_GP1_RVALID WREADY S_AXI_GP1_WREADY BRESP S_AXI_GP1_BRESP RRESP S_AXI_GP1_RRESP RDATA S_AXI_GP1_RDATA BID S_AXI_GP1_BID RID S_AXI_GP1_RID ARVALID S_AXI_GP1_ARVALID AWVALID S_AXI_GP1_AWVALID BREADY S_AXI_GP1_BREADY RREADY S_AXI_GP1_RREADY WLAST S_AXI_GP1_WLAST WVALID S_AXI_GP1_WVALID ARBURST S_AXI_GP1_ARBURST ARLOCK S_AXI_GP1_ARLOCK ARSIZE S_AXI_GP1_ARSIZE AWBURST S_AXI_GP1_AWBURST AWLOCK S_AXI_GP1_AWLOCK AWSIZE S_AXI_GP1_AWSIZE ARPROT S_AXI_GP1_ARPROT AWPROT S_AXI_GP1_AWPROT ARADDR S_AXI_GP1_ARADDR AWADDR S_AXI_GP1_AWADDR WDATA S_AXI_GP1_WDATA ARCACHE S_AXI_GP1_ARCACHE ARLEN S_AXI_GP1_ARLEN ARQOS S_AXI_GP1_ARQOS AWCACHE S_AXI_GP1_AWCACHE AWLEN S_AXI_GP1_AWLEN AWQOS S_AXI_GP1_AWQOS WSTRB S_AXI_GP1_WSTRB ARID S_AXI_GP1_ARID AWID S_AXI_GP1_AWID WID S_AXI_GP1_WID NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_HP0 ARREADY S_AXI_HP0_ARREADY AWREADY S_AXI_HP0_AWREADY BVALID S_AXI_HP0_BVALID RLAST S_AXI_HP0_RLAST RVALID S_AXI_HP0_RVALID WREADY S_AXI_HP0_WREADY BRESP S_AXI_HP0_BRESP RRESP S_AXI_HP0_RRESP BID S_AXI_HP0_BID RID S_AXI_HP0_RID RDATA S_AXI_HP0_RDATA ARVALID S_AXI_HP0_ARVALID AWVALID S_AXI_HP0_AWVALID BREADY S_AXI_HP0_BREADY RREADY S_AXI_HP0_RREADY WLAST S_AXI_HP0_WLAST WVALID S_AXI_HP0_WVALID ARBURST S_AXI_HP0_ARBURST ARLOCK S_AXI_HP0_ARLOCK ARSIZE S_AXI_HP0_ARSIZE AWBURST S_AXI_HP0_AWBURST AWLOCK S_AXI_HP0_AWLOCK AWSIZE S_AXI_HP0_AWSIZE ARPROT S_AXI_HP0_ARPROT AWPROT S_AXI_HP0_AWPROT ARADDR S_AXI_HP0_ARADDR AWADDR S_AXI_HP0_AWADDR ARCACHE S_AXI_HP0_ARCACHE ARLEN S_AXI_HP0_ARLEN ARQOS S_AXI_HP0_ARQOS AWCACHE S_AXI_HP0_AWCACHE AWLEN S_AXI_HP0_AWLEN AWQOS S_AXI_HP0_AWQOS ARID S_AXI_HP0_ARID AWID S_AXI_HP0_AWID WID S_AXI_HP0_WID WDATA S_AXI_HP0_WDATA WSTRB S_AXI_HP0_WSTRB NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_HP1 ARREADY S_AXI_HP1_ARREADY AWREADY S_AXI_HP1_AWREADY BVALID S_AXI_HP1_BVALID RLAST S_AXI_HP1_RLAST RVALID S_AXI_HP1_RVALID WREADY S_AXI_HP1_WREADY BRESP S_AXI_HP1_BRESP RRESP S_AXI_HP1_RRESP BID S_AXI_HP1_BID RID S_AXI_HP1_RID RDATA S_AXI_HP1_RDATA ARVALID S_AXI_HP1_ARVALID AWVALID S_AXI_HP1_AWVALID BREADY S_AXI_HP1_BREADY RREADY S_AXI_HP1_RREADY WLAST S_AXI_HP1_WLAST WVALID S_AXI_HP1_WVALID ARBURST S_AXI_HP1_ARBURST ARLOCK S_AXI_HP1_ARLOCK ARSIZE S_AXI_HP1_ARSIZE AWBURST S_AXI_HP1_AWBURST AWLOCK S_AXI_HP1_AWLOCK AWSIZE S_AXI_HP1_AWSIZE ARPROT S_AXI_HP1_ARPROT AWPROT S_AXI_HP1_AWPROT ARADDR S_AXI_HP1_ARADDR AWADDR S_AXI_HP1_AWADDR ARCACHE S_AXI_HP1_ARCACHE ARLEN S_AXI_HP1_ARLEN ARQOS S_AXI_HP1_ARQOS AWCACHE S_AXI_HP1_AWCACHE AWLEN S_AXI_HP1_AWLEN AWQOS S_AXI_HP1_AWQOS ARID S_AXI_HP1_ARID AWID S_AXI_HP1_AWID WID S_AXI_HP1_WID WDATA S_AXI_HP1_WDATA WSTRB S_AXI_HP1_WSTRB NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_HP2 ARREADY S_AXI_HP2_ARREADY AWREADY S_AXI_HP2_AWREADY BVALID S_AXI_HP2_BVALID RLAST S_AXI_HP2_RLAST RVALID S_AXI_HP2_RVALID WREADY S_AXI_HP2_WREADY BRESP S_AXI_HP2_BRESP RRESP S_AXI_HP2_RRESP BID S_AXI_HP2_BID RID S_AXI_HP2_RID RDATA S_AXI_HP2_RDATA ARVALID S_AXI_HP2_ARVALID AWVALID S_AXI_HP2_AWVALID BREADY S_AXI_HP2_BREADY RREADY S_AXI_HP2_RREADY WLAST S_AXI_HP2_WLAST WVALID S_AXI_HP2_WVALID ARBURST S_AXI_HP2_ARBURST ARLOCK S_AXI_HP2_ARLOCK ARSIZE S_AXI_HP2_ARSIZE AWBURST S_AXI_HP2_AWBURST AWLOCK S_AXI_HP2_AWLOCK AWSIZE S_AXI_HP2_AWSIZE ARPROT S_AXI_HP2_ARPROT AWPROT S_AXI_HP2_AWPROT ARADDR S_AXI_HP2_ARADDR AWADDR S_AXI_HP2_AWADDR ARCACHE S_AXI_HP2_ARCACHE ARLEN S_AXI_HP2_ARLEN ARQOS S_AXI_HP2_ARQOS AWCACHE S_AXI_HP2_AWCACHE AWLEN S_AXI_HP2_AWLEN AWQOS S_AXI_HP2_AWQOS ARID S_AXI_HP2_ARID AWID S_AXI_HP2_AWID WID S_AXI_HP2_WID WDATA S_AXI_HP2_WDATA WSTRB S_AXI_HP2_WSTRB NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false S_AXI_HP3 ARREADY S_AXI_HP3_ARREADY AWREADY S_AXI_HP3_AWREADY BVALID S_AXI_HP3_BVALID RLAST S_AXI_HP3_RLAST RVALID S_AXI_HP3_RVALID WREADY S_AXI_HP3_WREADY BRESP S_AXI_HP3_BRESP RRESP S_AXI_HP3_RRESP BID S_AXI_HP3_BID RID S_AXI_HP3_RID RDATA S_AXI_HP3_RDATA ARVALID S_AXI_HP3_ARVALID AWVALID S_AXI_HP3_AWVALID BREADY S_AXI_HP3_BREADY RREADY S_AXI_HP3_RREADY WLAST S_AXI_HP3_WLAST WVALID S_AXI_HP3_WVALID ARBURST S_AXI_HP3_ARBURST ARLOCK S_AXI_HP3_ARLOCK ARSIZE S_AXI_HP3_ARSIZE AWBURST S_AXI_HP3_AWBURST AWLOCK S_AXI_HP3_AWLOCK AWSIZE S_AXI_HP3_AWSIZE ARPROT S_AXI_HP3_ARPROT AWPROT S_AXI_HP3_AWPROT ARADDR S_AXI_HP3_ARADDR AWADDR S_AXI_HP3_AWADDR ARCACHE S_AXI_HP3_ARCACHE ARLEN S_AXI_HP3_ARLEN ARQOS S_AXI_HP3_ARQOS AWCACHE S_AXI_HP3_AWCACHE AWLEN S_AXI_HP3_AWLEN AWQOS S_AXI_HP3_AWQOS ARID S_AXI_HP3_ARID AWID S_AXI_HP3_AWID WID S_AXI_HP3_WID WDATA S_AXI_HP3_WDATA WSTRB S_AXI_HP3_WSTRB NUM_WRITE_OUTSTANDING NUM WRITE OUTSTANDING 8 NUM_READ_OUTSTANDING NUM READ OUTSTANDING 8 DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.0 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false FCLK_CLK0 CLK FCLK_CLK0 FREQ_HZ 1e+08 FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true FCLK_CLK1 CLK FCLK_CLK1 FREQ_HZ 1e+07 FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false FCLK_CLK2 CLK FCLK_CLK2 FREQ_HZ 1e+07 FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false FCLK_CLK3 CLK FCLK_CLK3 FREQ_HZ 1e+07 FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false FCLK_RESET0_N RST FCLK_RESET0_N POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl true FCLK_RESET1_N RST FCLK_RESET1_N POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl false FCLK_RESET2_N RST FCLK_RESET2_N POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl false FCLK_RESET3_N RST FCLK_RESET3_N POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl false IRQ_P2F_DMAC_ABORT INTERRUPT IRQ_P2F_DMAC_ABORT SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC0 INTERRUPT IRQ_P2F_DMAC0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC1 INTERRUPT IRQ_P2F_DMAC1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC2 INTERRUPT IRQ_P2F_DMAC2 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC3 INTERRUPT IRQ_P2F_DMAC3 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC4 INTERRUPT IRQ_P2F_DMAC4 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC5 INTERRUPT IRQ_P2F_DMAC5 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC6 INTERRUPT IRQ_P2F_DMAC6 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_DMAC7 INTERRUPT IRQ_P2F_DMAC7 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_SMC INTERRUPT IRQ_P2F_SMC SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_QSPI INTERRUPT IRQ_P2F_QSPI SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_CTI INTERRUPT IRQ_P2F_CTI SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_GPIO INTERRUPT IRQ_P2F_GPIO SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_USB0 INTERRUPT IRQ_P2F_USB0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_ENET0 INTERRUPT IRQ_P2F_ENET0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_ENET_WAKE0 INTERRUPT IRQ_P2F_ENET_WAKE0 SENSITIVITY EDGE_RISING PortWidth 1 none false IRQ_P2F_SDIO0 INTERRUPT IRQ_P2F_SDIO0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_I2C0 INTERRUPT IRQ_P2F_I2C0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_SPI0 INTERRUPT IRQ_P2F_SPI0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_UART0 INTERRUPT IRQ_P2F_UART0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_CAN0 INTERRUPT IRQ_P2F_CAN0 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_USB1 INTERRUPT IRQ_P2F_USB1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_ENET1 INTERRUPT IRQ_P2F_ENET1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_ENET_WAKE1 INTERRUPT IRQ_P2F_ENET_WAKE1 SENSITIVITY EDGE_RISING PortWidth 1 none false IRQ_P2F_SDIO1 INTERRUPT IRQ_P2F_SDIO1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_I2C1 INTERRUPT IRQ_P2F_I2C1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_SPI1 INTERRUPT IRQ_P2F_SPI1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_UART1 INTERRUPT IRQ_P2F_UART1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_P2F_CAN1 INTERRUPT IRQ_P2F_CAN1 SENSITIVITY LEVEL_HIGH PortWidth 1 none false IRQ_F2P INTERRUPT IRQ_F2P SENSITIVITY LEVEL_HIGH none PortWidth 1 none false Core0_nFIQ INTERRUPT Core0_nFIQ SENSITIVITY LEVEL_HIGH none PortWidth 1 none false Core0_nIRQ INTERRUPT Core0_nIRQ SENSITIVITY LEVEL_HIGH none PortWidth 1 none false Core1_nFIQ INTERRUPT Core1_nFIQ SENSITIVITY LEVEL_HIGH none PortWidth 1 none false Core1_nIRQ INTERRUPT Core1_nIRQ SENSITIVITY LEVEL_HIGH none PortWidth 1 none false M_AXI_GP0_ACLK CLK M_AXI_GP0_ACLK ASSOCIATED_BUSIF M_AXI_GP0 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false M_AXI_GP1_ACLK CLK M_AXI_GP1_ACLK ASSOCIATED_BUSIF M_AXI_GP1 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_ACP_ACLK CLK S_AXI_ACP_ACLK ASSOCIATED_BUSIF S_AXI_ACP FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_GP0_ACLK CLK S_AXI_GP0_ACLK ASSOCIATED_BUSIF S_AXI_GP0 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_GP1_ACLK CLK S_AXI_GP1_ACLK ASSOCIATED_BUSIF S_AXI_GP1 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_HP0_ACLK CLK S_AXI_HP0_ACLK ASSOCIATED_BUSIF S_AXI_HP0 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_HP1_ACLK CLK S_AXI_HP1_ACLK ASSOCIATED_BUSIF S_AXI_HP1 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_HP2_ACLK CLK S_AXI_HP2_ACLK ASSOCIATED_BUSIF S_AXI_HP2 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_AXI_HP3_ACLK CLK S_AXI_HP3_ACLK ASSOCIATED_BUSIF S_AXI_HP3 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false FTMD_TRACEIN_CLK CLK FTMD_TRACEIN_CLK ASSOCIATED_BUSIF FTM_TRACE_DATA FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false DMA0_ACLK CLK DMA0_ACLK ASSOCIATED_BUSIF DMA0_ACK:DMA0_REQ FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false DMA1_ACLK CLK DMA1_ACLK ASSOCIATED_BUSIF DMA1_ACK:DMA1_REQ FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false DMA2_ACLK CLK DMA2_ACLK ASSOCIATED_BUSIF DMA2_ACK:DMA2_REQ FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false DMA3_ACLK CLK DMA3_ACLK ASSOCIATED_BUSIF DMA3_ACK:DMA3_REQ FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.0 none CLK_DOMAIN none ASSOCIATED_PORT none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false TRIGGER_IN_0 TRIG FTMT_F2P_TRIG_0 ACK FTMT_F2P_TRIGACK_0 false TRIGGER_IN_1 TRIG FTMT_F2P_TRIG_1 ACK FTMT_F2P_TRIGACK_1 false TRIGGER_IN_2 TRIG FTMT_F2P_TRIG_2 ACK FTMT_F2P_TRIGACK_2 false TRIGGER_IN_3 TRIG FTMT_F2P_TRIG_3 ACK FTMT_F2P_TRIGACK_3 false TRIGGER_OUT_0 ACK FTMT_P2F_TRIGACK_0 TRIG FTMT_P2F_TRIG_0 false TRIGGER_OUT_1 ACK FTMT_P2F_TRIGACK_1 TRIG FTMT_P2F_TRIG_1 false TRIGGER_OUT_2 ACK FTMT_P2F_TRIGACK_2 TRIG FTMT_P2F_TRIG_2 false TRIGGER_OUT_3 ACK FTMT_P2F_TRIGACK_3 TRIG FTMT_P2F_TRIG_3 false M_AXI_GP0_tlm AXIMM_READ_SOCKET M_AXI_GP0_rd_socket AXIMM_WRITE_SOCKET M_AXI_GP0_wr_socket M_AXI_GP1_tlm AXIMM_READ_SOCKET M_AXI_GP1_rd_socket AXIMM_WRITE_SOCKET M_AXI_GP1_wr_socket S_AXI_GP0_tlm AXIMM_READ_SOCKET S_AXI_GP0_rd_socket AXIMM_WRITE_SOCKET S_AXI_GP0_wr_socket S_AXI_GP1_tlm AXIMM_READ_SOCKET S_AXI_GP1_rd_socket AXIMM_WRITE_SOCKET S_AXI_GP1_wr_socket S_AXI_GP2_tlm AXIMM_READ_SOCKET S_AXI_GP2_rd_socket AXIMM_WRITE_SOCKET S_AXI_GP2_wr_socket S_AXI_GP3_tlm AXIMM_READ_SOCKET S_AXI_GP3_rd_socket AXIMM_WRITE_SOCKET S_AXI_GP3_wr_socket S_AXI_ACP_tlm AXIMM_READ_SOCKET S_AXI_ACP_rd_socket AXIMM_WRITE_SOCKET S_AXI_ACP_wr_socket S_AXI_HP0_tlm AXIMM_READ_SOCKET S_AXI_HP0_rd_socket AXIMM_WRITE_SOCKET S_AXI_HP0_wr_socket S_AXI_HP1_tlm AXIMM_READ_SOCKET S_AXI_HP1_rd_socket AXIMM_WRITE_SOCKET S_AXI_HP1_wr_socket S_AXI_HP2_tlm AXIMM_READ_SOCKET S_AXI_HP2_rd_socket AXIMM_WRITE_SOCKET S_AXI_HP2_wr_socket S_AXI_HP3_tlm AXIMM_READ_SOCKET S_AXI_HP3_rd_socket AXIMM_WRITE_SOCKET S_AXI_HP3_wr_socket Data Data 4G 32 segment1 segment1 0x00000000 0x00040000 segment2 segment2 0x00040000 0x00040000 segment3 segment3 0x00080000 0x00080000 segment4 segment4 0x00100000 0x3ff00000 M_AXI_GP0 M_AXI_GP0 0x40000000 0x40000000 M_AXI_GP1 M_AXI_GP1 0x80000000 0x40000000 IO_Peripheral_Registers IO Peripheral Registers 0xe0000000 0x00300000 SMC_Memories SMC Memories 0xe1000000 0x05000000 SLCR_Registers SLCR Registers 0xf8000000 0x00000c00 PS_System_Registers PS System Registers 0xf8001000 0x0080f000 CPU_Private_Registers CPU Private Registers 0xf8900000 0x00603000 segment5 segment5 0xfc000000 0x02000000 segment6 segment6 0xfffc0000 0x00040000 S_AXI_HP0 HP0_LOW_OCM HP0 LOW OCM 0x00000000 0x00040000 32 memory false HP0_DDR_LOWOCM HP0 DDR LOWOCM 0x00000000 536870912 32 memory true HP0_HIGH_OCM HP0 HIGH OCM 0xfffc0000 0x00040000 32 memory false false S_AXI_HP1 HP1_LOW_OCM HP1 LOW OCM 0x00000000 0x00040000 32 memory false HP1_DDR_LOWOCM HP1 DDR LOWOCM 0x00000000 536870912 32 memory true HP1_HIGH_OCM HP1 HIGH OCM 0xfffc0000 0x00040000 32 memory false false S_AXI_HP2 HP2_LOW_OCM HP2 LOW OCM 0x00000000 0x00040000 32 memory false HP2_DDR_LOWOCM HP2 DDR LOWOCM 0x00000000 536870912 32 memory true HP2_HIGH_OCM HP2 HIGH OCM 0xfffc0000 0x00040000 32 memory false false S_AXI_HP3 HP3_LOW_OCM HP3 LOW OCM 0x00000000 0x00040000 32 memory false HP3_DDR_LOWOCM HP3 DDR LOWOCM 0x00000000 536870912 32 memory true HP3_HIGH_OCM HP3 HIGH OCM 0xfffc0000 0x00040000 32 memory false false S_AXI_GP0 GP0_LOW_OCM GP0 LOW OCM 0x00000000 0x00040000 32 memory false GP0_DDR_LOWOCM GP0 DDR LOWOCM 0x00000000 536870912 32 memory true GP0_HIGH_OCM GP0 HIGH OCM 0xfffc0000 0x00040000 32 memory false GP0_QSPI_LINEAR GP0 QSPI LINEAR 0xfc000000 16777216 32 memory false GP0_SRAM_NOR0 GP0 SRAM NOR 0 0xe2000000 0x02000000 32 memory false GP0_SRAM_NOR1 GP0 SRAM NOR 1 0xe4000000 0x02000000 32 memory false GP0_NAND GP0 NAND 0xe1000000 0x01000000 32 memory false GP0_IOP GP0 IOP 0xe0000000 0x00400000 32 register true GP0_UART0 GP0 UART0 0xe0000000 0x00001000 32 register false GP0_UART1 GP0 UART0 0xe0001000 0x00001000 32 register false GP0_USB0 GP0 USB0 0xe0002000 0x00001000 32 register false GP0_USB1 GP0 USB1 0xe0003000 0x00001000 32 register false GP0_IIC0 GP0 IIC0 0xe0004000 0x00001000 32 register false GP0_IIC1 GP0 IIC1 0xe0005000 0x00001000 32 register false GP0_SPI0 GP0 SPI0 0xe0006000 0x00001000 32 register false GP0_SPI1 GP0 SPI1 0xe0007000 0x00001000 32 register false GP0_CAN0 GP0 CAN0 0xe0008000 0x00001000 32 register false GP0_CAN1 GP0 CAN1 0xe0009000 0x00001000 32 register false GP0_GPIO GP0 GPIO 0xe000A000 0x00001000 32 register false GP0_ENET0 GP0 ENET0 0xe000B000 0x00001000 32 register false GP0_ENET1 GP0 ENET1 0xe000C000 0x00001000 32 register false GP0_QSPI GP0 QSPI 0xe000D000 0x00001000 32 register false GP0_SMC GP0 SMC 0xe000e000 0x00001000 32 register false GP0_SDIO0 GP0 SDIO0 0xe0100000 0x00001000 32 register false GP0_SDIO1 GP0 SDIO1 0xe0101000 0x00001000 32 register false GP0_PS_SLCR_REGS GP0 PS REG 0xf8000000 0x00010000 32 register false GP0_SLCR GP0 SLCR 0xf8000000 0x00001000 32 register false GP0_TTC0 GP0 TTC0 0xf8001000 0x00001000 32 register false GP0_TTC1 GP0 TTC1 0xf8002000 0x00001000 32 register false GP0_DMAC_S GP0 DMAC S 0xf8003000 0x00001000 32 register false GP0_DMAC_NS GP0 DMAC NS 0xf8004000 0x00001000 32 register false GP0_SWDT GP0 SWDT 0xf8005000 0x00001000 32 register false GP0_DDRC GP0 DDRC 0xf8006000 0x00001000 32 register false GP0_DEVCFG GP0 DEVCFG 0xf8007000 0x00001000 32 register false GP0_AFI0 GP0 AFI0 0xf8008000 0x00001000 32 register false GP0_AFI1 GP0 AFI1 0xf8009000 0x00001000 32 register false GP0_AFI2 GP0 AFI2 0xf800A000 0x00001000 32 register false GP0_AFI3 GP0 AFI3 0xf800B000 0x00001000 32 register false GP0_OCM_REG GP0 OCM REG 0xf800C000 0x00001000 32 register false GP0_CORESIGHT GP0 CORESIGHT 0xf8800000 0x00100000 32 register false GP0_M_AXI_GP0 GP0 M AXI GP0 0x40000000 0x40000000 32 register false GP0_M_AXI_GP1 GP0 M AXI GP1 0x80000000 0x40000000 32 register false false S_AXI_GP1 GP1_LOW_OCM GP1 LOW OCM 0x00000000 0x00040000 32 memory false GP1_DDR_LOWOCM GP1 DDR LOWOCM 0x00000000 536870912 32 memory true GP1_HIGH_OCM GP1 HIGH OCM 0xfffc0000 0x00040000 32 memory false GP1_QSPI_LINEAR GP1 QSPI LINEAR 0xfc000000 16777216 32 memory false GP1_SRAM_NOR0 GP1 SRAM NOR 0 0xe2000000 0x02000000 32 memory false GP1_SRAM_NOR1 GP1 SRAM NOR 1 0xe4000000 0x02000000 32 memory false GP1_NAND GP1 NAND 0xe1000000 0x01000000 32 memory false GP1_IOP GP1 IOP 0xe0000000 0x00400000 32 register true GP1_UART0 GP1 UART0 0xe0000000 0x00001000 32 register false GP1_UART1 GP1 UART0 0xe0001000 0x00001000 32 register false GP1_USB0 GP1 USB0 0xe0002000 0x00001000 32 register false GP1_USB1 GP1 USB1 0xe0003000 0x00001000 32 register false GP1_IIC0 GP1 IIC0 0xe0004000 0x00001000 32 register false GP1_IIC1 GP1 IIC1 0xe0005000 0x00001000 32 register false GP1_SPI0 GP1 SPI0 0xe0006000 0x00001000 32 register false GP1_SPI1 GP1 SPI1 0xe0007000 0x00001000 32 register false GP1_CAN0 GP1 CAN0 0xe0008000 0x00001000 32 register false GP1_CAN1 GP1 CAN1 0xe0009000 0x00001000 32 register false GP1_GPIO GP1 GPIO 0xe000A000 0x00001000 32 register false GP1_ENET0 GP1 ENET0 0xe000B000 0x00001000 32 register false GP1_ENET1 GP1 ENET1 0xe000C000 0x00001000 32 register false GP1_QSPI GP1 QSPI 0xe000D000 0x00001000 32 register false GP1_SMC GP1 SMC 0xe000e000 0x00001000 32 register false GP1_SDIO0 GP1 SDIO0 0xe0100000 0x00001000 32 register false GP1_SDIO1 GP1 SDIO1 0xe0101000 0x00001000 32 register false GP1_PS_SLCR_REGS GP1 PS REG 0xf8000000 0x00010000 32 register false GP1_SLCR GP1 SLCR 0xf8000000 0x00001000 32 register false GP1_TTC0 GP1 TTC0 0xf8001000 0x00001000 32 register false GP1_TTC1 GP1 TTC1 0xf8002000 0x00001000 32 register false GP1_DMAC_S GP1 DMAC S 0xf8003000 0x00001000 32 register false GP1_DMAC_NS GP1 DMAC NS 0xf8004000 0x00001000 32 register false GP1_SWDT GP1 SWDT 0xf8005000 0x00001000 32 register false GP1_DDRC GP1 DDRC 0xf8006000 0x00001000 32 register false GP1_DEVCFG GP1 DEVCFG 0xf8007000 0x00001000 32 register false GP1_AFI0 GP1 AFI0 0xf8008000 0x00001000 32 register false GP1_AFI1 GP1 AFI1 0xf8009000 0x00001000 32 register false GP1_AFI2 GP1 AFI2 0xf800A000 0x00001000 32 register false GP1_AFI3 GP1 AFI3 0xf800B000 0x00001000 32 register false GP1_OCM_REG GP1 OCM REG 0xf800C000 0x00001000 32 register false GP1_CORESIGHT GP1 CORESIGHT 0xf8800000 0x00100000 32 register false GP1_M_AXI_GP0 GP1 M AXI GP0 0x40000000 0x40000000 32 register false GP1_M_AXI_GP1 GP1 M AXI GP1 0x80000000 0x40000000 32 register false false S_AXI_ACP ACP_LOW_OCM ACP LOW OCM 0x00000000 0x00040000 32 memory false ACP_DDR_LOWOCM ACP DDR LOWOCM 0x00000000 536870912 32 memory true ACP_HIGH_OCM ACP HIGH OCM 0xfffc0000 0x00040000 32 memory false ACP_QSPI_LINEAR ACP QSPI LINEAR 0xfc000000 16777216 32 memory false ACP_SRAM_NOR0 ACP SRAM NOR 0 0xe2000000 0x02000000 32 memory false ACP_SRAM_NOR1 ACP SRAM NOR 1 0xe4000000 0x02000000 32 memory false ACP_NAND ACP NAND 0xe1000000 0x01000000 32 memory false ACP_IOP ACP IOP 0xe0000000 0x00400000 32 register true ACP_UART0 ACP UART0 0xe0000000 0x00001000 32 register false ACP_UART1 ACP UART0 0xe0001000 0x00001000 32 register false ACP_USB0 ACP USB0 0xe0002000 0x00001000 32 register false ACP_USB1 ACP USB1 0xe0003000 0x00001000 32 register false ACP_IIC0 ACP IIC0 0xe0004000 0x00001000 32 register false ACP_IIC1 ACP IIC1 0xe0005000 0x00001000 32 register false ACP_SPI0 ACP SPI0 0xe0006000 0x00001000 32 register false ACP_SPI1 ACP SPI1 0xe0007000 0x00001000 32 register false ACP_CAN0 ACP CAN0 0xe0008000 0x00001000 32 register false ACP_CAN1 ACP CAN1 0xe0009000 0x00001000 32 register false ACP_GPIO ACP GPIO 0xe000A000 0x00001000 32 register false ACP_ENET0 ACP ENET0 0xe000B000 0x00001000 32 register false ACP_ENET1 ACP ENET1 0xe000C000 0x00001000 32 register false ACP_QSPI ACP QSPI 0xe000D000 0x00001000 32 register false ACP_SMC ACP SMC 0xe000e000 0x00001000 32 register false ACP_SDIO0 ACP SDIO0 0xe0100000 0x00001000 32 register false ACP_SDIO1 ACP SDIO1 0xe0101000 0x00001000 32 register false ACP_PS_SLCR_REGS ACP PS REG 0xf8000000 0x00010000 32 register false ACP_SLCR ACP SLCR 0xf8000000 0x00001000 32 register false ACP_TTC0 ACP TTC0 0xf8001000 0x00001000 32 register false ACP_TTC1 ACP TTC1 0xf8002000 0x00001000 32 register false ACP_DMAC_S ACP DMAC S 0xf8003000 0x00001000 32 register false ACP_DMAC_NS ACP DMAC NS 0xf8004000 0x00001000 32 register false ACP_SWDT ACP SWDT 0xf8005000 0x00001000 32 register false ACP_DDRC ACP DDRC 0xf8006000 0x00001000 32 register false ACP_DEVCFG ACP DEVCFG 0xf8007000 0x00001000 32 register false ACP_AFI0 ACP AFI0 0xf8008000 0x00001000 32 register false ACP_AFI1 ACP AFI1 0xf8009000 0x00001000 32 register false ACP_AFI2 ACP AFI2 0xf800A000 0x00001000 32 register false ACP_AFI3 ACP AFI3 0xf800B000 0x00001000 32 register false ACP_OCM_REG ACP OCM REG 0xf800C000 0x00001000 32 register false ACP_CORESIGHT ACP CORESIGHT 0xf8800000 0x00100000 32 register false ACP_M_AXI_GP0 ACP M AXI GP0 0x40000000 0x40000000 32 register false ACP_M_AXI_GP1 ACP M AXI GP1 0x80000000 0x40000000 32 register false false xilinx_veriloginstantiationtemplate Verilog Instantiation Template verilogSource:vivado.xilinx.com:synthesis.template verilog xilinx_veriloginstantiationtemplate_view_fileset GENtimestamp Mon Sep 05 14:38:37 UTC 2022 outputProductCRC 9:740d5fc0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis processing_system7_v5_5_processing_system7 xilinx_anylanguagesynthesis_view_fileset GENtimestamp Mon Sep 05 14:38:49 UTC 2022 outputProductCRC 9:740d5fc0 xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints outputProductCRC 9:740d5fc0 xilinx_verilogsynthesiswrapper Verilog Synthesis Wrapper verilogSource:vivado.xilinx.com:synthesis.wrapper verilog zynqps xilinx_verilogsynthesiswrapper_view_fileset GENtimestamp Mon Sep 05 14:38:49 UTC 2022 outputProductCRC 9:740d5fc0 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation processing_system7_v1_0_processing_system7_vip xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_vip_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_vip_1_0__ref_view_fileset outputProductCRC 9:fdc37552 xilinx_systemcsimulation SystemC Simulation systemCSource:vivado.xilinx.com:simulation systemc processing_system7_v5_5_tlm xilinx_systemcsimulation_view_fileset GENtimestamp Mon Sep 05 14:38:49 UTC 2022 outputProductCRC 9:ba941ca4 sim_type tlm xilinx_anylanguagebehavioralsimulation_1 Simulation :vivado.xilinx.com:simulation processing_system7 xilinx_anylanguagebehavioralsimulation_1_view_fileset GENtimestamp Mon Sep 05 14:38:49 UTC 2022 outputProductCRC 9:fdc37552 sim_type tlm_dpi xilinx_anylanguagesimulationwrapper Simulation Wrapper :vivado.xilinx.com:simulation.wrapper zynqps xilinx_anylanguagesimulationwrapper_view_fileset GENtimestamp Mon Sep 05 14:38:49 UTC 2022 outputProductCRC 9:fdc37552 xilinx_systemcsimulationwrapper SystemC Simulation Wrapper systemCSource:vivado.xilinx.com:simulation.wrapper systemc zynqps xilinx_systemcsimulationwrapper_view_fileset GENtimestamp Mon Sep 05 14:38:49 UTC 2022 outputProductCRC 9:ba941ca4 sim_type tlm xilinx_anylanguagesimulationwrapper_1 Simulation Wrapper :vivado.xilinx.com:simulation.wrapper zynqps xilinx_anylanguagesimulationwrapper_1_view_fileset GENtimestamp Mon Sep 05 14:38:50 UTC 2022 outputProductCRC 9:fdc37552 sim_type tlm_dpi xilinx_project_archive Miscellaneous :vivado.xilinx.com:misc.files xilinx_project_archive_view_fileset GENtimestamp Mon Sep 05 14:38:50 UTC 2022 outputProductCRC 9:740d5fc0 xilinx_versioninformation Version Information :vivado.xilinx.com:docs.versioninfo xilinx_versioninformation_view_fileset GENtimestamp Mon Sep 05 14:38:50 UTC 2022 outputProductCRC 9:740d5fc0 xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon Sep 05 14:39:19 UTC 2022 outputProductCRC 9:740d5fc0 CAN0_PHY_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false CAN0_PHY_RX in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false CAN1_PHY_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false CAN1_PHY_RX in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_GMII_TX_EN out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_GMII_TX_ER out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_MDIO_MDC out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_MDIO_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_MDIO_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_DELAY_REQ_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_DELAY_REQ_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_PDELAY_REQ_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_PDELAY_REQ_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_PDELAY_RESP_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_PDELAY_RESP_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_SYNC_FRAME_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_PTP_SYNC_FRAME_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_SOF_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_SOF_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_GMII_TXD out 7 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_GMII_COL in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_GMII_CRS in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_GMII_RX_CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_GMII_RX_DV in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_GMII_RX_ER in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_GMII_TX_CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET0_MDIO_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_EXT_INTIN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET0_GMII_RXD in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_GMII_TX_EN out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_GMII_TX_ER out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_MDIO_MDC out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_MDIO_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_MDIO_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_DELAY_REQ_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_DELAY_REQ_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_PDELAY_REQ_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_PDELAY_REQ_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_PDELAY_RESP_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_PDELAY_RESP_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_SYNC_FRAME_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_PTP_SYNC_FRAME_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_SOF_RX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_SOF_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_GMII_TXD out 7 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_GMII_COL in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_GMII_CRS in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_GMII_RX_CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_GMII_RX_DV in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_GMII_RX_ER in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_GMII_TX_CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ENET1_MDIO_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_EXT_INTIN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false ENET1_GMII_RXD in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false GPIO_I in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false GPIO_O out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false GPIO_T out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C0_SDA_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false I2C0_SDA_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C0_SDA_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C0_SCL_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false I2C0_SCL_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C0_SCL_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C1_SDA_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false I2C1_SDA_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C1_SDA_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C1_SCL_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false I2C1_SCL_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false I2C1_SCL_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false PJTAG_TCK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false PJTAG_TMS in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false PJTAG_TDI in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false PJTAG_TDO out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_CLK out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_CLK_FB in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO0_CMD_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_CMD_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO0_CMD_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_DATA_I in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO0_DATA_O out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_DATA_T out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_LED out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_CDN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO0_WP in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO0_BUSPOW out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO0_BUSVOLT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_CLK out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_CLK_FB in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO1_CMD_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_CMD_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO1_CMD_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_DATA_I in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO1_DATA_O out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_DATA_T out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_LED out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_CDN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO1_WP in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SDIO1_BUSPOW out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SDIO1_BUSVOLT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_SCLK_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI0_SCLK_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_SCLK_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_MOSI_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI0_MOSI_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_MOSI_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_MISO_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI0_MISO_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_MISO_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_SS_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI0_SS_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_SS1_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_SS2_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI0_SS_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_SCLK_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI1_SCLK_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_SCLK_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_MOSI_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI1_MOSI_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_MOSI_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_MISO_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI1_MISO_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_MISO_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_SS_I in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SPI1_SS_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_SS1_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_SS2_O out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false SPI1_SS_T out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART0_DTRN out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART0_RTSN out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART0_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART0_CTSN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART0_DCDN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART0_DSRN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART0_RIN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART0_RX in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 false UART1_DTRN out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART1_RTSN out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART1_TX out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false UART1_CTSN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART1_DCDN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART1_DSRN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART1_RIN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false UART1_RX in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 false TTC0_WAVE0_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TTC0_WAVE1_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TTC0_WAVE2_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TTC0_CLK0_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false TTC0_CLK1_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false TTC0_CLK2_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false TTC1_WAVE0_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TTC1_WAVE1_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TTC1_WAVE2_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TTC1_CLK0_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false TTC1_CLK1_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false TTC1_CLK2_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false WDT_CLK_IN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false WDT_RST_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TRACE_CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false TRACE_CLK_OUT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TRACE_CTL out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false TRACE_DATA out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false USB0_PORT_INDCTL out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false USB0_VBUS_PWRSELECT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false USB0_VBUS_PWRFAULT in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false USB1_PORT_INDCTL out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false USB1_VBUS_PWRSELECT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false USB1_VBUS_PWRFAULT in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false SRAM_INTIN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_ARVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_BREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_RREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_WLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_WVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARID out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWID out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_WID out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARBURST out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARLOCK out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARSIZE out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWBURST out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWLOCK out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWSIZE out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARPROT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWPROT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARADDR out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWADDR out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_WDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARCACHE out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARLEN out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ARQOS out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWCACHE out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWLEN out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_AWQOS out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_WSTRB out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP0_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_ARREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_AWREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_BVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_RLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_RVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_WREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_BID in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_RID in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_BRESP in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_RRESP in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP0_RDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_ARVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_BREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_RREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_WLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_WVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARID out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWID out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_WID out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARBURST out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARLOCK out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARSIZE out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWBURST out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWLOCK out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWSIZE out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARPROT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWPROT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARADDR out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWADDR out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_WDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARCACHE out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARLEN out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ARQOS out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWCACHE out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWLEN out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_AWQOS out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_WSTRB out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false M_AXI_GP1_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_ARREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_AWREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_BVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_RLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_RVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_WREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_BID in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_RID in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_BRESP in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_RRESP in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false M_AXI_GP1_RDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_RDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_BID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_RID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP0_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_WDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_WSTRB in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_ARID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_AWID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP0_WID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_RDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_BID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_RID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_GP1_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_WDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_WSTRB in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_ARID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_AWID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_GP1_WID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_BID out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_RID out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_RDATA out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_ACP_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARID in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWID in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_WID in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_ARUSER in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_AWUSER in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_WDATA in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_ACP_WSTRB in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_BID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RDATA out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_WCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_RACOUNT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_WACOUNT out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP0_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_RDISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_WRISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_ARID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_AWID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_WID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_WDATA in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP0_WSTRB in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_BID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RDATA out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_WCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_RACOUNT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_WACOUNT out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP1_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_RDISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_WRISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_ARID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_AWID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_WID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_WDATA in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP1_WSTRB in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_BID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RDATA out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_WCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_RACOUNT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_WACOUNT out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP2_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_RDISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_WRISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_ARID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_AWID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_WID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_WDATA in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP2_WSTRB in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RLAST out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_BID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RID out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RDATA out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_WCOUNT out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_RACOUNT out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_WACOUNT out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false S_AXI_HP3_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_RDISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_WLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_WRISSUECAP1_EN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWBURST in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWLOCK in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWSIZE in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWADDR in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWCACHE in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWLEN in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWQOS in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_ARID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_AWID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_WID in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_WDATA in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_HP3_WSTRB in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false IRQ_P2F_DMAC_ABORT out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_DMAC7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_SMC out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_QSPI out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_CTI out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_GPIO out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_USB0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_ENET0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_ENET_WAKE0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_SDIO0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_I2C0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_SPI0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_UART0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_CAN0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_USB1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_ENET1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_ENET_WAKE1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_SDIO1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_I2C1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_SPI1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_UART1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_P2F_CAN1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false IRQ_F2P in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false Core0_nFIQ in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false Core0_nIRQ in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false Core1_nFIQ in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false Core1_nIRQ in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA0_DATYPE out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA0_DAVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA0_DRREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA1_DATYPE out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA1_DAVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA1_DRREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA2_DATYPE out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA2_DAVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA2_DRREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA3_DATYPE out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA3_DAVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA3_DRREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false DMA0_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA0_DAREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA0_DRLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA0_DRVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA1_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA1_DAREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA1_DRLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA1_DRVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA2_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA2_DAREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA2_DRLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA2_DRVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA3_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA3_DAREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA3_DRLAST in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA3_DRVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA0_DRTYPE in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA1_DRTYPE in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA2_DRTYPE in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DMA3_DRTYPE in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FCLK_CLK0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true FCLK_CLK1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FCLK_CLK2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FCLK_CLK3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FCLK_CLKTRIG0_N in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FCLK_CLKTRIG1_N in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FCLK_CLKTRIG2_N in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FCLK_CLKTRIG3_N in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FCLK_RESET0_N out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true FCLK_RESET1_N out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FCLK_RESET2_N out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FCLK_RESET3_N out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMD_TRACEIN_DATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMD_TRACEIN_VALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMD_TRACEIN_CLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMD_TRACEIN_ATID in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_F2P_TRIG_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_F2P_TRIGACK_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_F2P_TRIG_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_F2P_TRIGACK_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_F2P_TRIG_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_F2P_TRIGACK_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_F2P_TRIG_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_F2P_TRIGACK_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_F2P_DEBUG in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_P2F_TRIGACK_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_P2F_TRIG_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_P2F_TRIGACK_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_P2F_TRIG_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_P2F_TRIGACK_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_P2F_TRIG_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_P2F_TRIGACK_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false FTMT_P2F_TRIG_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FTMT_P2F_DEBUG out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false FPGA_IDLE_N in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false EVENT_EVENTO out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false EVENT_STANDBYWFE out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false EVENT_STANDBYWFI out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false EVENT_EVENTI in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false DDR_ARB in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false MIO inout 53 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DDR_CAS_n inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_CKE inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_Clk_n inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_Clk inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_CS_n inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_DRSTB inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_ODT inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_RAS_n inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_WEB inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_BankAddr inout 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_Addr inout 14 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_VRN inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_VRP inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_DM inout 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_DQ inout 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_DQS_n inout 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true DDR_DQS inout 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true PS_SRSTB inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation PS_CLK inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation PS_PORB inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_GP0_rd_socket xtlm::xtlm_aximm_initiator_socket xtlm.h requires tlm name rd_socket width 32 1 M_AXI_GP0_wr_socket xtlm::xtlm_aximm_initiator_socket xtlm.h requires tlm name wr_socket width 32 1 M_AXI_GP1_rd_socket xtlm::xtlm_aximm_initiator_socket xtlm.h requires tlm name rd_socket width 32 1 M_AXI_GP1_wr_socket xtlm::xtlm_aximm_initiator_socket xtlm.h requires tlm name wr_socket width 32 1 S_AXI_GP0_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_GP0_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_GP1_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_GP2_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_GP3_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_GP1_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_GP2_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_GP3_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_HP0_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_HP0_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_HP1_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_HP1_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_HP2_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_HP2_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_HP3_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_HP3_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 S_AXI_ACP_rd_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 32 1 S_AXI_ACP_wr_socket xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 32 1 C_EN_EMIO_PJTAG 0 C_EN_EMIO_ENET0 0 C_EN_EMIO_ENET1 0 C_EN_EMIO_TRACE 0 C_INCLUDE_TRACE_BUFFER 0 C_TRACE_BUFFER_FIFO_SIZE 128 USE_TRACE_DATA_EDGE_DETECTOR 0 C_TRACE_PIPELINE_WIDTH 8 C_TRACE_BUFFER_CLOCK_DELAY 12 C_EMIO_GPIO_WIDTH 64 C_INCLUDE_ACP_TRANS_CHECK 0 C_USE_DEFAULT_ACP_USER_VAL 0 C_S_AXI_ACP_ARUSER_VAL 31 C_S_AXI_ACP_AWUSER_VAL 31 C_M_AXI_GP0_ID_WIDTH 12 C_M_AXI_GP0_ENABLE_STATIC_REMAP 0 C_M_AXI_GP1_ID_WIDTH 12 C_M_AXI_GP1_ENABLE_STATIC_REMAP 0 C_S_AXI_GP0_ID_WIDTH 6 C_S_AXI_GP1_ID_WIDTH 6 C_S_AXI_ACP_ID_WIDTH 3 C_S_AXI_HP0_ID_WIDTH 6 C_S_AXI_HP0_DATA_WIDTH 64 C_S_AXI_HP1_ID_WIDTH 6 C_S_AXI_HP1_DATA_WIDTH 64 C_S_AXI_HP2_ID_WIDTH 6 C_S_AXI_HP2_DATA_WIDTH 64 C_S_AXI_HP3_ID_WIDTH 6 C_S_AXI_HP3_DATA_WIDTH 64 C_M_AXI_GP0_THREAD_ID_WIDTH 12 C_M_AXI_GP1_THREAD_ID_WIDTH 12 C_NUM_F2P_INTR_INPUTS 1 C_IRQ_F2P_MODE DIRECT C_DQ_WIDTH 32 C_DQS_WIDTH 4 C_DM_WIDTH 4 C_MIO_PRIMITIVE 54 C_TRACE_INTERNAL_WIDTH 2 C_USE_AXI_NONSECURE 0 C_USE_M_AXI_GP0 0 C_USE_M_AXI_GP1 0 C_USE_S_AXI_GP0 0 C_USE_S_AXI_GP1 0 C_USE_S_AXI_HP0 0 C_USE_S_AXI_HP1 0 C_USE_S_AXI_HP2 0 C_USE_S_AXI_HP3 0 C_USE_S_AXI_ACP 0 C_PS7_SI_REV PRODUCTION C_FCLK_CLK0_BUF TRUE C_FCLK_CLK1_BUF FALSE C_FCLK_CLK2_BUF FALSE C_FCLK_CLK3_BUF FALSE C_PACKAGE_NAME clg400 C_GP0_EN_MODIFIABLE_TXN 1 C_GP1_EN_MODIFIABLE_TXN 1 choice_list_020b381d <Select> MIO 40 .. 51 choice_list_070fff2f 1 2 3 4 5 6 7 8 choice_list_0d7de060 ARM PLL DDR PLL IO PLL External choice_list_0f5c91ba EMIO MIO 8 .. 9 MIO 12 .. 13 MIO 16 .. 17 MIO 20 .. 21 MIO 24 .. 25 MIO 28 .. 29 MIO 32 .. 33 MIO 36 .. 37 MIO 40 .. 41 MIO 44 .. 45 MIO 48 .. 49 MIO 52 .. 53 choice_list_1075ca33 4 2 choice_list_129b798f <Select> EMIO MIO 18 MIO 30 MIO 42 choice_list_1a80fa5a <Select> EMIO MIO 18 .. 19 MIO 30 .. 31 MIO 42 .. 43 choice_list_1e4fa2cf <Select> MIO choice_list_2091a159 <Select> MIO 0 2.. 14 choice_list_20dc6536 32 16 choice_list_2328412a HPR(0)/LPR(32) HPR(8)/LPR(24) HPR(16)/LPR(16) HPR(24)/LPR(8) HPR(32)/LPR(0) choice_list_27376075 12 choice_list_2d7daef4 disabled enabled choice_list_2e355d8b Normal (0-85) High (95 Max) choice_list_303d848a <Select> MIO 1 choice_list_30d18a73 0xE0105fff choice_list_319636fe 0xE0104fff choice_list_31d1d296 <Select> DISABLED CPU0 DBG_ACK CPU1 DBG_ACK BOTH choice_list_32c7371b 128 MBits 256 MBits 512 MBits 1024 MBits 2048 MBits 4096 MBits 8192 MBits choice_list_353a343d <Select> MIO 3 .. 39 choice_list_35b40bd0 6 choice_list_3607bdd0 0xE0102fff choice_list_3740015d 0xE0103fff choice_list_390b0393 <Select> EMIO MIO 16 .. 21 MIO 28 .. 33 MIO 40 .. 45 choice_list_3b9f1944 <Select> x8 choice_list_3c74058c <Select> MIO 0 MIO 2 MIO 4 MIO 6 MIO 8 MIO 10 MIO 12 MIO 14 MIO 16 MIO 18 MIO 20 MIO 22 MIO 24 MIO 26 MIO 28 MIO 30 MIO 32 MIO 34 MIO 36 MIO 38 MIO 40 MIO 42 MIO 44 MIO 46 MIO 48 MIO 50 MIO 52 choice_list_3f5f808e LVCMOS 3.3V LVCMOS 2.5V HSTL 1.8V LVCMOS 1.8V choice_list_422ff54b <Select> fast slow choice_list_45a0fd9c <Select> EMIO MIO 14 .. 15 MIO 26 .. 27 choice_list_46eb370a DIRECT REVERSE choice_list_49727578 0x00100000 0x00040000 choice_list_4d36a164 <Select> Low Medium High choice_list_56c426e3 <Select> in out inout choice_list_56e9f994 <Select> EMIO MIO 10 .. 13 MIO 22 .. 25 MIO 34 .. 37 MIO 46 .. 49 choice_list_5d0f73c4 <Select> EMIO MIO 10 .. 11 MIO 14 .. 15 MIO 18 .. 19 MIO 22 .. 23 MIO 26 .. 27 MIO 30 .. 31 MIO 34 .. 35 MIO 38 .. 39 MIO 42 .. 43 MIO 46 .. 47 MIO 50 .. 51 choice_list_5d70a6b7 <Select> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 choice_list_606c1634 <Select> EMIO MIO 52 .. 53 choice_list_6727dfa6 1 0 choice_list_6a282484 <Select> EMIO MIO 0 MIO 1 MIO 2 MIO 3 MIO 4 MIO 5 MIO 6 MIO 9 MIO 10 MIO 11 MIO 12 MIO 13 MIO 14 MIO 15 MIO 16 MIO 17 MIO 18 MIO 19 MIO 20 MIO 21 MIO 22 MIO 23 MIO 24 MIO 25 MIO 26 MIO 27 MIO 28 MIO 29 MIO 30 MIO 31 MIO 32 MIO 33 MIO 34 MIO 35 MIO 36 MIO 37 MIO 38 MIO 39 MIO 40 MIO 41 MIO 42 MIO 43 MIO 44 MIO 45 MIO 46 MIO 47 MIO 48 MIO 49 MIO 50 MIO 51 MIO 52 MIO 53 choice_list_6bc4d474 LVCMOS 3.3V choice_list_6bd7fb73 Active High Active Low choice_list_7275faaa <Select> LVCMOS 3.3V choice_list_72f3e128 LVCMOS 1.8V LVCMOS 2.5V LVCMOS 3.3V HSTL 1.8V choice_list_767f870c External choice_list_7abc2131 16 Bit 32 Bit choice_list_7bfdc3d8 <Select> EMIO MIO 20 MIO 32 MIO 44 choice_list_7d098ed6 ARM PLL IO PLL DDR PLL External choice_list_7d6d1b3f 1 2 3 choice_list_7f27baa5 DDR3_800D DDR3_800E DDR3_1066E DDR3_1066F DDR3_1066G DDR3_1333F DDR3_1333G DDR3_1333H DDR3_1333J DDR3_1600G DDR3_1600H DDR3_1600J DDR3_1600K choice_list_82c3921b 0xE0008FFF choice_list_83072ce2 <Select> MIO 1 MIO 3 MIO 5 MIO 7 MIO 9 MIO 11 MIO 13 MIO 15 MIO 17 MIO 19 MIO 21 MIO 23 MIO 25 MIO 27 MIO 29 MIO 31 MIO 33 MIO 35 MIO 37 MIO 39 MIO 41 MIO 43 MIO 45 MIO 47 MIO 49 MIO 51 MIO 53 choice_list_83842e96 0xE0009FFF choice_list_85a6bbc3 <Select> DISABLED CPU0 DBG_REQ CPU1 DBG_REQ BOTH choice_list_86458347 fast slow choice_list_86fc01e0 <Select> EMIO MIO 16 .. 27 choice_list_88a617f1 <Select> EMIO MIO 12 .. 13 MIO 16 .. 17 MIO 20 .. 21 MIO 24 .. 25 MIO 28 .. 29 MIO 32 .. 33 MIO 36 .. 37 MIO 40 .. 41 MIO 44 .. 45 MIO 48 .. 49 MIO 52 .. 53 choice_list_88fe7673 0xE0000FFF choice_list_893462de <Select> EMIO MIO 8 .. 9 MIO 12 .. 13 MIO 16 .. 17 MIO 20 .. 21 MIO 24 .. 25 MIO 28 .. 29 MIO 32 .. 33 MIO 36 .. 37 MIO 40 .. 41 MIO 44 .. 45 MIO 48 .. 49 MIO 52 .. 53 choice_list_89b9cafe 0xE0001FFF choice_list_8af5a703 0 1 choice_list_8ca738ca 0xE0005FFF choice_list_8de08447 0xE0004FFF choice_list_8e2841d0 0xE0007FFF choice_list_8f6ffd5d 0xE0006FFF choice_list_908f40dd <Select> EMIO MIO 16 .. 19 choice_list_92aefd84 0xE0104000 choice_list_935a3e6e <Select> EMIO MIO 12 .. 13 MIO 24 .. 25 choice_list_93a2bb4f <Select> EMIO MIO 13 MIO 25 MIO 37 MIO 49 choice_list_93e94109 0xE0105000 choice_list_9478ca27 0xE0103000 choice_list_953f76aa 0xE0102000 choice_list_95a9da0c in out inout choice_list_96d47178 <Select> EMIO MIO 14 MIO 26 MIO 38 MIO 50 choice_list_96d47805 32 64 128 256 choice_list_96f7b33d 0xE0101000 choice_list_97b00fb0 0xE0100000 choice_list_99ba8646 32 64 choice_list_9e358632 None Default ZC702 ZC706 ZedBoard choice_list_a0318123 54 32 choice_list_a0c775a9 clg484 clg225 clg400 ffg676 fbg676 fbg484 ffg900 cl400 cl484 rf676 fb484 choice_list_a841b9a1 1000 Mbps 100 Mbps 10 Mbps choice_list_a8e6d6fb <Select> EMIO MIO 14 .. 15 MIO 26 .. 27 MIO 38 .. 39 MIO 50 .. 51 MIO 52 .. 53 choice_list_ae9f88f6 1 choice_list_af9e7a8f <Select> EMIO MIO 10 .. 11 MIO 22 .. 23 choice_list_b3ee7919 <Select> EMIO MIO 0 MIO 1 MIO 2 MIO 3 MIO 4 MIO 5 MIO 6 MIO 7 MIO 8 MIO 9 MIO 10 MIO 11 MIO 12 MIO 13 MIO 14 MIO 15 MIO 16 MIO 17 MIO 18 MIO 19 MIO 20 MIO 21 MIO 22 MIO 23 MIO 24 MIO 25 MIO 26 MIO 27 MIO 28 MIO 29 MIO 30 MIO 31 MIO 32 MIO 33 MIO 34 MIO 35 MIO 36 MIO 37 MIO 38 MIO 39 MIO 40 MIO 41 MIO 42 MIO 43 MIO 44 MIO 45 MIO 46 MIO 47 MIO 48 MIO 49 MIO 50 MIO 51 MIO 52 MIO 53 choice_list_b4a6147c 0xE000B000 choice_list_b5e1a8f1 0xE000C000 choice_list_b66926f4 <Select> EMIO MIO 28 .. 39 choice_list_b6ff1ce3 <Select> EMIO MIO 15 MIO 27 MIO 39 MIO 51 choice_list_b76ed1eb 0xE000A000 choice_list_ba65fe0e <Select> EMIO MIO 2 .. 9 choice_list_bc805c93 <Select> x1 x2 x4 choice_list_bd8e4b31 6:2:1 4:2:1 choice_list_be8ca58c MT41J128M8 JP-125 MT41J128M8 JP-15E MT41J64M16 JT-125G MT41J64M16 JT-15E MT41J256M8 DA-107 MT41K128M16 JT-125 MT41J256M8 HX-125 MT41J256M8 HX-15E MT41J256M8 HX-187E MT41J128M16 HA-107G MT41J128M16 HA-125 MT41J128M16 HA-15E MT41J128M16 HA-187E MT41J512M8 RA-15E MT41K128M16 HA-15E MT41K256M16 RE-125 MT41K256M16 RE-15E MT41K256M8 DA-125 MT41K256M8 DA-15E MT41K256M8 HX-15E MT41J256M16 RE-125 Custom choice_list_bed41605 PRODUCTION choice_list_c11320b6 0x3FFFFFFF choice_list_c4046e95 0xE0100FFF choice_list_c543d218 0xE0101FFF choice_list_c5ebb0ea LPDDR 2 DDR 2 DDR 3 DDR 3 (Low Voltage) choice_list_ca108395 2 4 8 16 32 choice_list_ce8c471b <Select> disabled enabled choice_list_d0304fb3 0xE0009000 choice_list_d10f4555 FALSE TRUE choice_list_d177f33e 0xE0008000 choice_list_d282f9a2 <Select> EMIO MIO 16 .. 17 MIO 28 .. 29 MIO 40 .. 41 choice_list_d2a5f697 CPU_1X External choice_list_d2f51b63 <Select> MIO 0 9 .. 13 choice_list_d525dd8e 0xFCFFFFFF choice_list_d54f49f9 <Select> MIO 28 .. 39 choice_list_d679c87d <Select> MIO 0 MIO 1 MIO 2 MIO 3 MIO 4 MIO 5 MIO 6 MIO 7 MIO 8 MIO 9 MIO 10 MIO 11 MIO 12 MIO 13 MIO 14 MIO 15 MIO 16 MIO 17 MIO 18 MIO 19 MIO 20 MIO 21 MIO 22 MIO 23 MIO 24 MIO 25 MIO 26 MIO 27 MIO 28 MIO 29 MIO 30 MIO 31 MIO 32 MIO 33 MIO 34 MIO 35 MIO 36 MIO 37 MIO 38 MIO 39 MIO 40 MIO 41 MIO 42 MIO 43 MIO 44 MIO 45 MIO 46 MIO 47 MIO 48 MIO 49 MIO 50 MIO 51 MIO 52 MIO 53 choice_list_d88af9c3 <Select> Share reset pin Separate reset pins choice_list_da0dabdb 0xE0001000 choice_list_db4a1756 0xE0000000 choice_list_dc7979fd <Select> MIO 8 choice_list_dc85a6c5 ARM PLL DDR PLL External IO PLL choice_list_dcdb9c78 0xE0006000 choice_list_dd9c20f5 0xE0007000 choice_list_de54e562 0xE0004000 choice_list_de6d24b0 <Select> MIO 1 .. 6 choice_list_df1359ef 0xE0005000 choice_list_e14dbfa8 <Select> MIO 0 choice_list_e4dab0ce 0xE000AFFF choice_list_e655c9d4 0xE000CFFF choice_list_e7127559 0xE000BFFF choice_list_e743b0fa DDR PLL choice_list_ea556125 ARM PLL DDR PLL IO PLL choice_list_eaad72ce 8 Bits 16 Bits 32 Bits choice_list_f192fb1e <Select> EMIO MIO 19 MIO 31 MIO 43 choice_list_f585525a 110 300 1200 2400 4800 9600 19200 38400 57600 115200 128000 230400 460800 921600 choice_list_f591e16e DDR PLL ARM PLL IO PLL choice_list_f5e7200e 6 12 choice_list_f7022b26 <Select> EMIO MIO 10 .. 15 MIO 22 .. 27 MIO 34 .. 39 MIO 46 .. 51 choice_list_f7b6ff1b <Select> EMIO choice_list_fb1b25ef <Select> MIO 16 .. 23 choice_list_fc3456a9 Disabled Enabled choice_list_fd37a6fb 4 8 choice_list_fe5d5471 <Select> Share reset pin xilinx_veriloginstantiationtemplate_view_fileset zynqps.vho vhdlTemplate zynqps.veo verilogTemplate xilinx_anylanguagesynthesis_view_fileset zynqps.xdc xdc processing_order early hdl/verilog/zynqps.hwdef hwdef USED_IN_hw_handoff ps7_init.c cSource USED_IN_hw_handoff ps7_init.h cSource USED_IN_hw_handoff ps7_init_gpl.c cSource USED_IN_hw_handoff ps7_init_gpl.h cSource USED_IN_hw_handoff ps7_init.tcl tclSource USED_IN_hw_handoff ps7_init.html html USED_IN_hw_handoff hdl/verilog/processing_system7_v5_5_aw_atc.v verilogSource hdl/verilog/processing_system7_v5_5_b_atc.v verilogSource hdl/verilog/processing_system7_v5_5_w_atc.v verilogSource hdl/verilog/processing_system7_v5_5_atc.v verilogSource hdl/verilog/processing_system7_v5_5_trace_buffer.v verilogSource hdl/verilog/processing_system7_v5_5_processing_system7.v verilogSource xilinx_verilogsynthesiswrapper_view_fileset synth/zynqps.v verilogSource xil_defaultlib xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset hdl/axi_infrastructure_v1_1_0.vh verilogSource USED_IN_ipstatic true axi_infrastructure_v1_1_0 hdl/axi_infrastructure_v1_1_vl_rfs.v verilogSource USED_IN_ipstatic axi_infrastructure_v1_1_0 xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_vip_1_1__ref_view_fileset hdl/axi_vip_v1_1_vl_rfs.sv systemVerilogSource USED_IN_ipstatic axi_vip_v1_1_11 xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_vip_1_0__ref_view_fileset hdl/processing_system7_vip_v1_0_13_local_params.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_vl_rfs.sv systemVerilogSource USED_IN_ipstatic processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_reg_params.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_reg_init.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_apis.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_unused_ports.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_axi_gp.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_axi_acp.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 hdl/processing_system7_vip_v1_0_13_axi_hp.v verilogSource USED_IN_ipstatic true processing_system7_vip_v1_0_13 xilinx_systemcsimulation_view_fileset sim_tlm/processing_system7_v5_5_tlm.h systemCSource true sim_tlm/processing_system7_v5_5_tlm.cpp systemCSource sim_tlm/xilinx-zynq.h systemCSource USED_IN_ipstatic true processing_system7_v5_5_6 QEMU wrapper header file sim_tlm/b_transport_converter.h systemCSource USED_IN_ipstatic true processing_system7_v5_5_6 B2NB Transport Converter sim_tlm/xilinx-zynq.cc systemCSource USED_IN_ipstatic processing_system7_v5_5_6 QEMU wrapper src file xilinx_anylanguagebehavioralsimulation_1_view_fileset sim/libps7.so swObjectLibrary USED_IN_simulation sim/libps7.dll swObjectLibrary USED_IN_simulation sim/libremoteport.so swObjectLibrary USED_IN_simulation sim/libremoteport.dll swObjectLibrary USED_IN_simulation xilinx_anylanguagesimulationwrapper_view_fileset sim/zynqps.v verilogSource xilinx_systemcsimulationwrapper_view_fileset sim/zynqps_sc.h systemCSource true sim/zynqps_sc.cpp systemCSource sim/zynqps.h systemCSource true sim/zynqps.cpp systemCSource sim/zynqps_stub.sv systemVerilogSource xilinx_anylanguagesimulationwrapper_1_view_fileset sim/zynqps.sv systemVerilogSource xilinx_project_archive_view_fileset fixedio.xml xml fixedio_rtl.xml xml hpstatusctrl.xml xml hpstatusctrl_rtl.xml xml usbctrl.xml xml usbctrl_rtl.xml xml xilinx_versioninformation_view_fileset doc/processing_system7_v5_5_changelog.txt text xilinx_externalfiles_view_fileset zynqps.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib zynqps_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib zynqps_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib zynqps_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib zynqps_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib CPU0_A9 is_visible FALSE processor_type ARM CPU1_A9 is_visible FALSE processor_type ARM Arm dual core SOC with Zynq fpga PCW_DDR_RAM_BASEADDR PCW DDR RAM BASEADDR 0x00100000 true PCW_DDR_RAM_HIGHADDR PCW DDR RAM HIGHADDR 0x1FFFFFFF true PCW_UART0_BASEADDR PCW UART0 BASEADDR 0xE0000000 false PCW_UART0_HIGHADDR PCW UART0 HIGHADDR 0xE0000FFF false PCW_UART1_BASEADDR PCW UART1 BASEADDR 0xE0001000 true PCW_UART1_HIGHADDR PCW UART1 HIGHADDR 0xE0001FFF true PCW_I2C0_BASEADDR PCW I2C0 BASEADDR 0xE0004000 false PCW_I2C0_HIGHADDR PCW I2C0 HIGHADDR 0xE0004FFF false PCW_I2C1_BASEADDR PCW I2C1 BASEADDR 0xE0005000 false PCW_I2C1_HIGHADDR PCW I2C1 HIGHADDR 0xE0005FFF false PCW_SPI0_BASEADDR PCW SPI0 BASEADDR 0xE0006000 false PCW_SPI0_HIGHADDR PCW SPI0 HIGHADDR 0xE0006FFF false PCW_SPI1_BASEADDR PCW SPI1 BASEADDR 0xE0007000 false PCW_SPI1_HIGHADDR PCW SPI1 HIGHADDR 0xE0007FFF false PCW_CAN0_BASEADDR PCW CAN0 BASEADDR 0xE0008000 false PCW_CAN0_HIGHADDR PCW CAN0 HIGHADDR 0xE0008FFF false PCW_CAN1_BASEADDR PCW CAN1 BASEADDR 0xE0009000 false PCW_CAN1_HIGHADDR PCW CAN1 HIGHADDR 0xE0009FFF false PCW_GPIO_BASEADDR PCW GPIO BASEADDR 0xE000A000 false PCW_GPIO_HIGHADDR PCW GPIO HIGHADDR 0xE000AFFF false PCW_ENET0_BASEADDR PCW ENET0 BASEADDR 0xE000B000 false PCW_ENET0_HIGHADDR PCW ENET0 HIGHADDR 0xE000BFFF false PCW_ENET1_BASEADDR PCW ENET1 BASEADDR 0xE000C000 false PCW_ENET1_HIGHADDR PCW ENET1 HIGHADDR 0xE000CFFF false PCW_SDIO0_BASEADDR PCW SDIO0 BASEADDR 0xE0100000 false PCW_SDIO0_HIGHADDR PCW SDIO0 HIGHADDR 0xE0100FFF false PCW_SDIO1_BASEADDR PCW SDIO1 BASEADDR 0xE0101000 false PCW_SDIO1_HIGHADDR PCW SDIO1 HIGHADDR 0xE0101FFF false PCW_USB0_BASEADDR PCW USB0 BASEADDR 0xE0102000 false PCW_USB0_HIGHADDR PCW USB0 HIGHADDR 0xE0102fff false PCW_USB1_BASEADDR PCW USB1 BASEADDR 0xE0103000 false PCW_USB1_HIGHADDR PCW USB1 HIGHADDR 0xE0103fff false PCW_TTC0_BASEADDR PCW TTC0 BASEADDR 0xE0104000 false PCW_TTC0_HIGHADDR PCW TTC0 HIGHADDR 0xE0104fff false PCW_TTC1_BASEADDR PCW TTC1 BASEADDR 0xE0105000 false PCW_TTC1_HIGHADDR PCW TTC1 HIGHADDR 0xE0105fff false PCW_FCLK_CLK0_BUF PCW FCLK CLK0 BUF TRUE true PCW_FCLK_CLK1_BUF PCW FCLK CLK1 BUF FALSE false PCW_FCLK_CLK2_BUF PCW FCLK CLK2 BUF FALSE false PCW_FCLK_CLK3_BUF PCW FCLK CLK3 BUF FALSE false PCW_UIPARAM_DDR_FREQ_MHZ PCW UIPARAM DDR FREQ MHZ 533.333333 PCW_UIPARAM_DDR_BANK_ADDR_COUNT PCW UIPARAM DDR BANK ADDR COUNT 3 false PCW_UIPARAM_DDR_ROW_ADDR_COUNT PCW UIPARAM DDR ROW ADDR COUNT 15 false PCW_UIPARAM_DDR_COL_ADDR_COUNT PCW UIPARAM DDR COL ADDR COUNT 10 false PCW_UIPARAM_DDR_CL PCW UIPARAM DDR CL 7 false PCW_UIPARAM_DDR_CWL PCW UIPARAM DDR CWL 6 false PCW_UIPARAM_DDR_T_RCD PCW UIPARAM DDR T RCD 7 false PCW_UIPARAM_DDR_T_RP PCW UIPARAM DDR T RP 7 false PCW_UIPARAM_DDR_T_RC PCW UIPARAM DDR T RC 48.75 false PCW_UIPARAM_DDR_T_RAS_MIN PCW UIPARAM DDR T RAS MIN 35.0 false PCW_UIPARAM_DDR_T_FAW PCW UIPARAM DDR T FAW 40.0 false PCW_UIPARAM_DDR_AL PCW UIPARAM DDR AL 0 PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 PCW UIPARAM DDR DQS TO CLK DELAY 0 0.0 PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 PCW UIPARAM DDR DQS TO CLK DELAY 1 0.0 PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 PCW UIPARAM DDR DQS TO CLK DELAY 2 0.0 PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 PCW UIPARAM DDR DQS TO CLK DELAY 3 0.0 PCW_UIPARAM_DDR_BOARD_DELAY0 PCW UIPARAM DDR BOARD DELAY0 0.25 PCW_UIPARAM_DDR_BOARD_DELAY1 PCW UIPARAM DDR BOARD DELAY1 0.25 PCW_UIPARAM_DDR_BOARD_DELAY2 PCW UIPARAM DDR BOARD DELAY2 0.25 PCW_UIPARAM_DDR_BOARD_DELAY3 PCW UIPARAM DDR BOARD DELAY3 0.25 PCW_UIPARAM_DDR_DQS_0_LENGTH_MM PCW UIPARAM DDR DQS 0 LENGTH MM 0 PCW_UIPARAM_DDR_DQS_1_LENGTH_MM PCW UIPARAM DDR DQS 1 LENGTH MM 0 PCW_UIPARAM_DDR_DQS_2_LENGTH_MM PCW UIPARAM DDR DQS 2 LENGTH MM 0 PCW_UIPARAM_DDR_DQS_3_LENGTH_MM PCW UIPARAM DDR DQS 3 LENGTH MM 0 PCW_UIPARAM_DDR_DQ_0_LENGTH_MM PCW UIPARAM DDR DQ 0 LENGTH MM 0 PCW_UIPARAM_DDR_DQ_1_LENGTH_MM PCW UIPARAM DDR DQ 1 LENGTH MM 0 PCW_UIPARAM_DDR_DQ_2_LENGTH_MM PCW UIPARAM DDR DQ 2 LENGTH MM 0 PCW_UIPARAM_DDR_DQ_3_LENGTH_MM PCW UIPARAM DDR DQ 3 LENGTH MM 0 PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM PCW UIPARAM DDR CLOCK 0 LENGTH MM 0 PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM PCW UIPARAM DDR CLOCK 1 LENGTH MM 0 PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM PCW UIPARAM DDR CLOCK 2 LENGTH MM 0 PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM PCW UIPARAM DDR CLOCK 3 LENGTH MM 0 PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH PCW UIPARAM DDR DQS 0 PACKAGE LENGTH 101.239 PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH PCW UIPARAM DDR DQS 1 PACKAGE LENGTH 79.5025 PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH PCW UIPARAM DDR DQS 2 PACKAGE LENGTH 60.536 PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH PCW UIPARAM DDR DQS 3 PACKAGE LENGTH 71.7715 PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH PCW UIPARAM DDR DQ 0 PACKAGE LENGTH 104.5365 PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH PCW UIPARAM DDR DQ 1 PACKAGE LENGTH 70.676 PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH PCW UIPARAM DDR DQ 2 PACKAGE LENGTH 59.1615 PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH PCW UIPARAM DDR DQ 3 PACKAGE LENGTH 81.319 PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH 54.563 PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH 54.563 PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH 54.563 PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH 54.563 PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY PCW UIPARAM DDR DQS 0 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY PCW UIPARAM DDR DQS 1 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY PCW UIPARAM DDR DQS 2 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY PCW UIPARAM DDR DQS 3 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY PCW UIPARAM DDR DQ 0 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY PCW UIPARAM DDR DQ 1 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY PCW UIPARAM DDR DQ 2 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY PCW UIPARAM DDR DQ 3 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY 160 PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY 160 PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 PCW PACKAGE DDR DQS TO CLK DELAY 0 -0.047 PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 PCW PACKAGE DDR DQS TO CLK DELAY 1 -0.025 PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 PCW PACKAGE DDR DQS TO CLK DELAY 2 -0.006 PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 PCW PACKAGE DDR DQS TO CLK DELAY 3 -0.017 PCW_PACKAGE_DDR_BOARD_DELAY0 PCW PACKAGE DDR BOARD DELAY0 0.080 PCW_PACKAGE_DDR_BOARD_DELAY1 PCW PACKAGE DDR BOARD DELAY1 0.063 PCW_PACKAGE_DDR_BOARD_DELAY2 PCW PACKAGE DDR BOARD DELAY2 0.057 PCW_PACKAGE_DDR_BOARD_DELAY3 PCW PACKAGE DDR BOARD DELAY3 0.068 PCW_CPU_CPU_6X4X_MAX_RANGE PCW CPU CPU 6X4X MAX RANGE 767 PCW_CRYSTAL_PERIPHERAL_FREQMHZ PCW CRYSTAL PERIPHERAL FREQMHZ 33.333333 PCW_APU_PERIPHERAL_FREQMHZ PCW APU PERIPHERAL FREQMHZ 666.666666 PCW_DCI_PERIPHERAL_FREQMHZ PCW DCI PERIPHERAL FREQMHZ 10.159 PCW_QSPI_PERIPHERAL_FREQMHZ PCW QSPI PERIPHERAL FREQMHZ 200 false PCW_SMC_PERIPHERAL_FREQMHZ PCW SMC PERIPHERAL FREQMHZ 100 false PCW_USB0_PERIPHERAL_FREQMHZ PCW USB0 PERIPHERAL FREQMHZ 60 false PCW_USB1_PERIPHERAL_FREQMHZ PCW USB1 PERIPHERAL FREQMHZ 60 false PCW_SDIO_PERIPHERAL_FREQMHZ PCW SDIO PERIPHERAL FREQMHZ 100 false PCW_UART_PERIPHERAL_FREQMHZ PCW UART PERIPHERAL FREQMHZ 100 PCW_SPI_PERIPHERAL_FREQMHZ PCW SPI PERIPHERAL FREQMHZ 166.666666 false PCW_CAN_PERIPHERAL_FREQMHZ PCW CAN PERIPHERAL FREQMHZ 100 false PCW_CAN0_PERIPHERAL_FREQMHZ PCW CAN0 PERIPHERAL FREQMHZ -1 false PCW_CAN1_PERIPHERAL_FREQMHZ PCW CAN1 PERIPHERAL FREQMHZ -1 false PCW_I2C_PERIPHERAL_FREQMHZ PCW I2C PERIPHERAL FREQMHZ 25 false PCW_WDT_PERIPHERAL_FREQMHZ PCW WDT PERIPHERAL FREQMHZ 133.333333 false PCW_TTC_PERIPHERAL_FREQMHZ PCW TTC PERIPHERAL FREQMHZ 50 false PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ PCW TTC0 CLK0 PERIPHERAL FREQMHZ 133.333333 false PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ PCW TTC0 CLK1 PERIPHERAL FREQMHZ 133.333333 false PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ PCW TTC0 CLK2 PERIPHERAL FREQMHZ 133.333333 false PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ PCW TTC1 CLK0 PERIPHERAL FREQMHZ 133.333333 false PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ PCW TTC1 CLK1 PERIPHERAL FREQMHZ 133.333333 false PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ PCW TTC1 CLK2 PERIPHERAL FREQMHZ 133.333333 false PCW_PCAP_PERIPHERAL_FREQMHZ PCW PCAP PERIPHERAL FREQMHZ 200 PCW_TPIU_PERIPHERAL_FREQMHZ PCW TPIU PERIPHERAL FREQMHZ 200 false PCW_FPGA0_PERIPHERAL_FREQMHZ PCW FPGA0 PERIPHERAL FREQMHZ 100 PCW_FPGA1_PERIPHERAL_FREQMHZ PCW FPGA1 PERIPHERAL FREQMHZ 50 PCW_FPGA2_PERIPHERAL_FREQMHZ PCW FPGA2 PERIPHERAL FREQMHZ 50 PCW_FPGA3_PERIPHERAL_FREQMHZ PCW FPGA3 PERIPHERAL FREQMHZ 50 PCW_ACT_APU_PERIPHERAL_FREQMHZ PCW ACT APU PERIPHERAL FREQMHZ 666.666687 PCW_UIPARAM_ACT_DDR_FREQ_MHZ PCW UIPARAM ACT DDR FREQ MHZ 533.333374 PCW_ACT_DCI_PERIPHERAL_FREQMHZ PCW ACT DCI PERIPHERAL FREQMHZ 10.158730 PCW_ACT_QSPI_PERIPHERAL_FREQMHZ PCW ACT QSPI PERIPHERAL FREQMHZ 10.000000 PCW_ACT_SMC_PERIPHERAL_FREQMHZ PCW ACT SMC PERIPHERAL FREQMHZ 10.000000 PCW_ACT_ENET0_PERIPHERAL_FREQMHZ PCW ACT ENET0 PERIPHERAL FREQMHZ 10.000000 PCW_ACT_ENET1_PERIPHERAL_FREQMHZ PCW ACT ENET1 PERIPHERAL FREQMHZ 10.000000 PCW_ACT_USB0_PERIPHERAL_FREQMHZ PCW ACT USB0 PERIPHERAL FREQMHZ 60 PCW_ACT_USB1_PERIPHERAL_FREQMHZ PCW ACT USB1 PERIPHERAL FREQMHZ 60 PCW_ACT_SDIO_PERIPHERAL_FREQMHZ PCW ACT SDIO PERIPHERAL FREQMHZ 10.000000 PCW_ACT_UART_PERIPHERAL_FREQMHZ PCW ACT UART PERIPHERAL FREQMHZ 100.000000 PCW_ACT_SPI_PERIPHERAL_FREQMHZ PCW ACT SPI PERIPHERAL FREQMHZ 10.000000 PCW_ACT_CAN_PERIPHERAL_FREQMHZ PCW ACT CAN PERIPHERAL FREQMHZ 10.000000 PCW_ACT_CAN0_PERIPHERAL_FREQMHZ PCW ACT CAN0 PERIPHERAL FREQMHZ 23.8095 PCW_ACT_CAN1_PERIPHERAL_FREQMHZ PCW ACT CAN0 PERIPHERAL FREQMHZ 23.8095 PCW_ACT_I2C_PERIPHERAL_FREQMHZ PCW ACT I2C PERIPHERAL FREQMHZ 50 PCW_ACT_WDT_PERIPHERAL_FREQMHZ PCW ACT WDT PERIPHERAL FREQMHZ 111.111115 PCW_ACT_TTC_PERIPHERAL_FREQMHZ PCW ACT TTC PERIPHERAL FREQMHZ 50 PCW_ACT_PCAP_PERIPHERAL_FREQMHZ PCW ACT PCAP PERIPHERAL FREQMHZ 200.000000 PCW_ACT_TPIU_PERIPHERAL_FREQMHZ PCW ACT TPIU PERIPHERAL FREQMHZ 200.000000 PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ PCW ACT FPGA0 PERIPHERAL FREQMHZ 100.000000 PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ PCW ACT FPGA1 PERIPHERAL FREQMHZ 10.000000 PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ PCW ACT FPGA2 PERIPHERAL FREQMHZ 10.000000 PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ PCW ACT FPGA3 PERIPHERAL FREQMHZ 10.000000 PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ 111.111115 PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ 111.111115 PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ 111.111115 PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ 111.111115 PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ 111.111115 PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ 111.111115 PCW_CLK0_FREQ PCW CLK0 FREQ 100000000 PCW_CLK1_FREQ PCW CLK1 FREQ 10000000 PCW_CLK2_FREQ PCW CLK2 FREQ 10000000 PCW_CLK3_FREQ PCW CLK3 FREQ 10000000 PCW_OVERRIDE_BASIC_CLOCK PCW OVERRIDE FREQ 0 PCW_CPU_PERIPHERAL_DIVISOR0 CLKPARAM 2 false PCW_DDR_PERIPHERAL_DIVISOR0 CLKPARAM 2 false PCW_SMC_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_QSPI_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_SDIO_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_UART_PERIPHERAL_DIVISOR0 CLKPARAM 18 false PCW_SPI_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_CAN_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_CAN_PERIPHERAL_DIVISOR1 CLKPARAM 1 false PCW_FCLK0_PERIPHERAL_DIVISOR0 CLKPARAM 6 false PCW_FCLK1_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_FCLK2_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_FCLK3_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_FCLK0_PERIPHERAL_DIVISOR1 CLKPARAM 3 false PCW_FCLK1_PERIPHERAL_DIVISOR1 CLKPARAM 1 false PCW_FCLK2_PERIPHERAL_DIVISOR1 CLKPARAM 1 false PCW_FCLK3_PERIPHERAL_DIVISOR1 CLKPARAM 1 false PCW_ENET0_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_ENET1_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_ENET0_PERIPHERAL_DIVISOR1 CLKPARAM 1 false PCW_ENET1_PERIPHERAL_DIVISOR1 CLKPARAM 1 false PCW_TPIU_PERIPHERAL_DIVISOR0 CLKPARAM 1 false PCW_DCI_PERIPHERAL_DIVISOR0 CLKPARAM 15 false PCW_DCI_PERIPHERAL_DIVISOR1 CLKPARAM 7 false PCW_PCAP_PERIPHERAL_DIVISOR0 CLKPARAM 9 false PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_WDT_PERIPHERAL_DIVISOR0 CLKPARAM 1 PCW_ARMPLL_CTRL_FBDIV CLKPARAM 40 false PCW_IOPLL_CTRL_FBDIV CLKPARAM 54 false PCW_DDRPLL_CTRL_FBDIV CLKPARAM 32 false PCW_CPU_CPU_PLL_FREQMHZ CLKPARAM 1333.333 false PCW_IO_IO_PLL_FREQMHZ CLKPARAM 1800.000 false PCW_DDR_DDR_PLL_FREQMHZ CLKPARAM 1066.667 false PCW_SMC_PERIPHERAL_VALID PCW SMC PERIPHERAL VALID 0 PCW_SDIO_PERIPHERAL_VALID PCW SDIO PERIPHERAL VALID 0 PCW_SPI_PERIPHERAL_VALID PCW SPI PERIPHERAL VALID 0 PCW_CAN_PERIPHERAL_VALID PCW CAN PERIPHERAL VALID 0 PCW_UART_PERIPHERAL_VALID PCW UART PERIPHERAL VALID 1 PCW_EN_EMIO_CAN0 PCW EN EMIO CAN0 0 PCW_EN_EMIO_CAN1 PCW EN EMIO CAN1 0 PCW_EN_EMIO_ENET0 PCW EN EMIO ENET0 0 PCW_EN_EMIO_ENET1 PCW EN EMIO ENET1 0 PCW_EN_PTP_ENET0 PCW EN PTP ENET0 0 PCW_EN_PTP_ENET1 PCW EN PTP ENET1 0 PCW_EN_EMIO_GPIO PCW EN EMIO GPIO 0 PCW_EN_EMIO_I2C0 PCW EN EMIO I2C0 0 PCW_EN_EMIO_I2C1 PCW EN EMIO I2C1 0 PCW_EN_EMIO_PJTAG PCW EN EMIO PJTAG 0 PCW_EN_EMIO_SDIO0 PCW EN EMIO SDIO0 0 PCW_EN_EMIO_CD_SDIO0 PCW EN EMIO CD SDIO0 0 PCW_EN_EMIO_WP_SDIO0 PCW EN EMIO WP SDIO0 0 PCW_EN_EMIO_SDIO1 PCW EN EMIO SDIO1 0 PCW_EN_EMIO_CD_SDIO1 PCW EN EMIO CD SDIO1 0 PCW_EN_EMIO_WP_SDIO1 PCW EN EMIO WP SDIO1 0 PCW_EN_EMIO_SPI0 PCW EN EMIO SPI0 0 PCW_EN_EMIO_SPI1 PCW EN EMIO SPI1 0 PCW_EN_EMIO_UART0 PCW EN EMIO UART0 0 PCW_EN_EMIO_UART1 PCW EN EMIO UART1 0 PCW_EN_EMIO_MODEM_UART0 PCW EN EMIO MODEM UART0 0 PCW_EN_EMIO_MODEM_UART1 PCW EN EMIO MODEM UART1 0 PCW_EN_EMIO_TTC0 PCW EN EMIO TTC0 0 PCW_EN_EMIO_TTC1 PCW EN EMIO TTC1 0 PCW_EN_EMIO_WDT PCW EN EMIO WDT 0 PCW_EN_EMIO_TRACE PCW EN EMIO TRACE 0 PCW_USE_AXI_NONSECURE PCW USE AXI NON SECURE 0 PCW_USE_M_AXI_GP0 PCW USE M AXI GP0 0 PCW_USE_M_AXI_GP1 PCW USE M AXI GP1 0 PCW_USE_S_AXI_GP0 PCW USE S AXI GP0 0 PCW_USE_S_AXI_GP1 PCW USE S AXI GP1 0 PCW_USE_S_AXI_ACP PCW USE S AXI ACP 0 PCW_USE_S_AXI_HP0 PCW USE S AXI HP0 0 PCW_USE_S_AXI_HP1 PCW USE S AXI HP1 0 PCW_USE_S_AXI_HP2 PCW USE S AXI HP2 0 PCW_USE_S_AXI_HP3 PCW USE S AXI HP3 0 PCW_M_AXI_GP0_FREQMHZ PCW M AXI GP0 FREQMHZ 10 false PCW_M_AXI_GP1_FREQMHZ PCW M AXI GP1 FREQMHZ 10 false PCW_S_AXI_GP0_FREQMHZ PCW S AXI GP0 FREQMHZ 10 false PCW_S_AXI_GP1_FREQMHZ PCW S AXI GP1 FREQMHZ 10 false PCW_S_AXI_ACP_FREQMHZ PCW S AXI ACP FREQMHZ 10 false PCW_S_AXI_HP0_FREQMHZ PCW S AXI HP0 FREQMHZ 10 false PCW_S_AXI_HP1_FREQMHZ PCW S AXI HP1 FREQMHZ 10 false PCW_S_AXI_HP2_FREQMHZ PCW S AXI HP2 FREQMHZ 10 false PCW_S_AXI_HP3_FREQMHZ PCW S AXI HP3 FREQMHZ 10 false PCW_USE_DMA0 PCW USE DMA0 0 PCW_USE_DMA1 PCW USE DMA1 0 PCW_USE_DMA2 PCW USE DMA2 0 PCW_USE_DMA3 PCW USE DMA3 0 PCW_USE_TRACE PCW USE TRACE Enable FTM Trace interface used to capture data from PL to PS debug system 0 PCW_TRACE_PIPELINE_WIDTH PCW TRACE PIPELINE WIDTH 8 false PCW_INCLUDE_TRACE_BUFFER PCW INCLUDE TRACE BUFFER 0 false PCW_TRACE_BUFFER_FIFO_SIZE PCW TRACE BUFFER FIFO SIZE 128 false PCW_USE_TRACE_DATA_EDGE_DETECTOR PCW USE TRACE DATA EDGE DETECTOR 0 false PCW_TRACE_BUFFER_CLOCK_DELAY PCW TRACE BUFFER CLOCK DELAY 12 false PCW_USE_CROSS_TRIGGER PCW USE CROSS TRIGGER 0 PCW_FTM_CTI_IN0 <Select> false PCW_FTM_CTI_IN1 <Select> false PCW_FTM_CTI_IN2 <Select> false PCW_FTM_CTI_IN3 <Select> false PCW_FTM_CTI_OUT0 <Select> false PCW_FTM_CTI_OUT1 <Select> false PCW_FTM_CTI_OUT2 <Select> false PCW_FTM_CTI_OUT3 <Select> false PCW_USE_DEBUG PCW USE DEBUG 0 PCW_USE_CR_FABRIC PCW USE CR FABRIC 1 PCW_USE_AXI_FABRIC_IDLE PCW USE AXI FABRIC IDLE Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL 0 PCW_USE_DDR_BYPASS PCW USE DDR BYPASS Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller 0 PCW_USE_FABRIC_INTERRUPT PCW USE FABRIC INTERRUPT 0 PCW_USE_PROC_EVENT_BUS PCW USE PROC EVENT BUS 0 PCW_USE_EXPANDED_IOP PCW USE EXPANDED IOP 0 PCW_USE_HIGH_OCM PCW USE HIGH OCM 0 PCW_USE_PS_SLCR_REGISTERS PCW USE PS SLCR REGISTERS 0 PCW_USE_EXPANDED_PS_SLCR_REGISTERS PCW USE EXPANDED PS SLCR REGISTERS 0 false PCW_USE_CORESIGHT PCW USE CORESIGHT 0 PCW_EN_EMIO_SRAM_INT PCW EN EMIO SRAM INT 0 PCW_GPIO_EMIO_GPIO_WIDTH PCW EMIO GPIO WIDTH 64 false PCW_GP0_NUM_WRITE_THREADS GP0 NUM WRITE THREADS 4 PCW_GP0_NUM_READ_THREADS GP0 NUM READ THREADS 4 PCW_GP1_NUM_WRITE_THREADS GP1 NUM WRITE THREADS 4 PCW_GP1_NUM_READ_THREADS GP1 NUM READ THREADS 4 PCW_UART0_BAUD_RATE PCW UART0 BAUD RATE Configure baud rate to determine UART0 operating frequency 115200 false PCW_UART1_BAUD_RATE PCW UART1 BAUD RATE Configure baud rate to determine UART1 operating frequency 115200 true PCW_EN_4K_TIMER PCW EN 4K TIMER 0 PCW_M_AXI_GP0_ID_WIDTH PCW M AXI GP0 ID WIDTH 12 false PCW_M_AXI_GP0_ENABLE_STATIC_REMAP PCW M AXI GP0 ENABLE STATIC REMAP 0 false PCW_M_AXI_GP0_SUPPORT_NARROW_BURST PCW M AXI GP0 SUPPORT NARROW BURST 0 false PCW_M_AXI_GP0_THREAD_ID_WIDTH PCW M AXI GP0 THREAD ID WIDTH 12 false PCW_M_AXI_GP1_ID_WIDTH PCW M AXI GP1 ID WIDTH 12 false PCW_M_AXI_GP1_ENABLE_STATIC_REMAP PCW M AXI GP1 ENABLE STATIC REMAP 0 false PCW_M_AXI_GP1_SUPPORT_NARROW_BURST PCW M AXI GP1 SUPPORT NARROW BURST 0 false PCW_M_AXI_GP1_THREAD_ID_WIDTH PCW M AXI GP1 THREAD ID WIDTH 12 false PCW_S_AXI_GP0_ID_WIDTH PCW S AXI GP0 ID WIDTH 6 false PCW_S_AXI_GP1_ID_WIDTH PCW S AXI GP1 ID WIDTH 6 false PCW_S_AXI_ACP_ID_WIDTH PCW S AXI ACP ID WIDTH 3 false PCW_INCLUDE_ACP_TRANS_CHECK PCW INCLUDE ACP TRANS CHECK 0 PCW_USE_DEFAULT_ACP_USER_VAL PCW USE DEFAULT ACP USER VAL 0 false PCW_S_AXI_ACP_ARUSER_VAL PCW S AXI ACP ARUSER VAL 31 false PCW_S_AXI_ACP_AWUSER_VAL PCW S AXI ACP AWUSER VAL 31 false PCW_S_AXI_HP0_ID_WIDTH PCW S AXI HP0 ID WIDTH 6 false PCW_S_AXI_HP0_DATA_WIDTH PCW S AXI HP0 DATA WIDTH 64 false PCW_S_AXI_HP1_ID_WIDTH PCW S AXI HP1 ID WIDTH 6 false PCW_S_AXI_HP1_DATA_WIDTH PCW S AXI HP1 DATA WIDTH 64 false PCW_S_AXI_HP2_ID_WIDTH PCW S AXI HP2 ID WIDTH 6 false PCW_S_AXI_HP2_DATA_WIDTH PCW S AXI HP2 DATA WIDTH 64 false PCW_S_AXI_HP3_ID_WIDTH PCW S AXI HP3 ID WIDTH 6 false PCW_S_AXI_HP3_DATA_WIDTH PCW S AXI HP3 DATA WIDTH 64 false PCW_NUM_F2P_INTR_INPUTS PCW NUM F2P INTR INPUTS 1 false PCW_EN_DDR PCW EN DDR 1 PCW_EN_SMC PCW EN SMC 0 PCW_EN_QSPI PCW EN QSPI 0 PCW_EN_CAN0 PCW EN CAN0 0 PCW_EN_CAN1 PCW EN CAN1 0 PCW_EN_ENET0 PCW EN ENET0 0 PCW_EN_ENET1 PCW EN ENET1 0 PCW_EN_GPIO PCW EN GPIO 0 PCW_EN_I2C0 PCW EN I2C0 0 PCW_EN_I2C1 PCW EN I2C1 0 PCW_EN_PJTAG PCW EN PJTAG 0 PCW_EN_SDIO0 PCW EN SDIO0 0 PCW_EN_SDIO1 PCW EN SDIO1 0 PCW_EN_SPI0 PCW EN SPI0 0 PCW_EN_SPI1 PCW EN SPI1 0 PCW_EN_UART0 PCW EN UART0 0 PCW_EN_UART1 PCW EN UART1 1 PCW_EN_MODEM_UART0 PCW EN MODEM UART0 0 PCW_EN_MODEM_UART1 PCW EN MODEM UART1 0 PCW_EN_TTC0 PCW EN TTC0 0 PCW_EN_TTC1 PCW EN TTC1 0 PCW_EN_WDT PCW EN WDT 0 PCW_EN_TRACE PCW EN TRACE 0 PCW_EN_USB0 PCW EN USB0 0 PCW_EN_USB1 PCW EN USB1 0 PCW_DQ_WIDTH PCW DQ WIDTH 32 PCW_DQS_WIDTH PCW DQS WIDTH 4 PCW_DM_WIDTH PCW DM WIDTH 4 PCW_MIO_PRIMITIVE PCW MIO PRIMITIVE 54 PCW_EN_CLK0_PORT PCW EN CLK0 PORT 1 true PCW_EN_CLK1_PORT PCW EN CLK1 PORT 0 true PCW_EN_CLK2_PORT PCW EN CLK2 PORT 0 true PCW_EN_CLK3_PORT PCW EN CLK3 PORT 0 true PCW_EN_RST0_PORT PCW EN RST0 PORT Enables general purpose reset signal 0 for PL logic 1 true PCW_EN_RST1_PORT PCW EN RST1 PORT Enables general purpose reset signal 1 for PL logic 0 true PCW_EN_RST2_PORT PCW EN RST2 PORT Enables general purpose reset signal 2 for PL logic 0 true PCW_EN_RST3_PORT PCW EN RST3 PORT Enables general purpose reset signal 3 for PL logic 0 true PCW_EN_CLKTRIG0_PORT PCW EN CLKTRIG0 PORT Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses 0 true PCW_EN_CLKTRIG1_PORT PCW EN CLKTRIG1 PORT Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses 0 true PCW_EN_CLKTRIG2_PORT PCW EN CLKTRIG2 PORT Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses 0 true PCW_EN_CLKTRIG3_PORT PCW EN CLKTRIG3 PORT Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses 0 true PCW_P2F_DMAC_ABORT_INTR PCW P2F DMAC ABORT INTR 0 false PCW_P2F_DMAC0_INTR PCW P2F DMAC0 INTR 0 false PCW_P2F_DMAC1_INTR PCW P2F DMAC1 INTR 0 false PCW_P2F_DMAC2_INTR PCW P2F DMAC2 INTR 0 false PCW_P2F_DMAC3_INTR PCW P2F DMAC3 INTR 0 false PCW_P2F_DMAC4_INTR PCW P2F DMAC4 INTR 0 false PCW_P2F_DMAC5_INTR PCW P2F DMAC5 INTR 0 false PCW_P2F_DMAC6_INTR PCW P2F DMAC6 INTR 0 false PCW_P2F_DMAC7_INTR PCW P2F DMAC7 INTR 0 false PCW_P2F_SMC_INTR PCW P2F SMC INTR 0 false PCW_P2F_QSPI_INTR PCW P2F QSPI INTR 0 false PCW_P2F_CTI_INTR PCW P2F CTI INTR 0 false PCW_P2F_GPIO_INTR PCW P2F GPIO INTR 0 false PCW_P2F_USB0_INTR PCW P2F USB0 INTR 0 false PCW_P2F_ENET0_INTR PCW P2F ENET0 INTR 0 false PCW_P2F_SDIO0_INTR PCW P2F SDIO0 INTR 0 false PCW_P2F_I2C0_INTR PCW P2F I2C0 INTR 0 false PCW_P2F_SPI0_INTR PCW P2F SPI0 INTR 0 false PCW_P2F_UART0_INTR PCW P2F UART0 INTR 0 false PCW_P2F_CAN0_INTR PCW P2F CAN0 INTR 0 false PCW_P2F_USB1_INTR PCW P2F USB1 INTR 0 false PCW_P2F_ENET1_INTR PCW P2F ENET1 INTR 0 false PCW_P2F_SDIO1_INTR PCW P2F SDIO1 INTR 0 false PCW_P2F_I2C1_INTR PCW P2F I2C1 INTR 0 false PCW_P2F_SPI1_INTR PCW P2F SPI1 INTR 0 false PCW_P2F_UART1_INTR PCW P2F UART1 INTR 0 false PCW_P2F_CAN1_INTR PCW P2F CAN1 INTR 0 false PCW_IRQ_F2P_INTR PCW IRQ F2P INTR 0 false PCW_IRQ_F2P_MODE PCW IRQ F2P MODE DIRECT false PCW_CORE0_FIQ_INTR PCW CORE0 FIQ INTR 0 false PCW_CORE0_IRQ_INTR PCW CORE0 IRQ INTR 0 false PCW_CORE1_FIQ_INTR PCW CORE1 FIQ INTR 0 false PCW_CORE1_IRQ_INTR PCW CORE1 IRQ INTR 0 false PCW_VALUE_SILVERSION PCW VALUE SILVERSION 3 PCW_GP0_EN_MODIFIABLE_TXN PCW GP0 EN MODIFIABLE TXN 1 PCW_GP1_EN_MODIFIABLE_TXN PCW GP1 EN MODIFIABLE TXN 1 PCW_IMPORT_BOARD_PRESET PCW IMPORT BOARD PRESET None PCW_PERIPHERAL_BOARD_PRESET PCW PERIPHERAL BOARD PRESET None PCW_PRESET_BANK0_VOLTAGE PCW PRESET BANK0 VOLTAGE LVCMOS 3.3V PCW_PRESET_BANK1_VOLTAGE PCW PRESET BANK1 VOLTAGE LVCMOS 3.3V PCW_UIPARAM_DDR_ENABLE PCW UIPARAM DDR ENABLE 1 PCW_UIPARAM_DDR_ADV_ENABLE PCW UIPARAM DDR ADV ENABLE 0 PCW_UIPARAM_DDR_MEMORY_TYPE PCW UIPARAM DDR MEMORY TYPE DDR 3 PCW_UIPARAM_DDR_ECC PCW UIPARAM DDR ECC Disabled PCW_UIPARAM_DDR_BUS_WIDTH PCW UIPARAM DDR BUS WIDTH 16 Bit PCW_UIPARAM_DDR_BL PCW UIPARAM DDR BL 8 PCW_UIPARAM_DDR_HIGH_TEMP PCW UIPARAM DDR HIGH TEMP Normal (0-85) PCW_UIPARAM_DDR_PARTNO PCW UIPARAM DDR PARTNO MT41K256M16 RE-125 PCW_UIPARAM_DDR_DRAM_WIDTH PCW UIPARAM DDR DRAM WIDTH 16 Bits false PCW_UIPARAM_DDR_DEVICE_CAPACITY PCW UIPARAM DDR DEVICE CAPACITY 4096 MBits false PCW_UIPARAM_DDR_SPEED_BIN PCW UIPARAM DDR SPEED BIN DDR3_1066F false PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL PCW UIPARAM DDR TRAIN WRITE LEVEL 1 PCW_UIPARAM_DDR_TRAIN_READ_GATE PCW UIPARAM DDR TRAIN READ GATE 1 PCW_UIPARAM_DDR_TRAIN_DATA_EYE PCW UIPARAM DDR TRAIN DATA EYE 1 PCW_UIPARAM_DDR_CLOCK_STOP_EN PCW UIPARAM DDR CLOCK STOP EN 0 PCW_UIPARAM_DDR_USE_INTERNAL_VREF PCW UIPARAM DDR USE INTERNAL VREF 0 PCW_DDR_PRIORITY_WRITEPORT_0 PCW DDR PRIORITY WRITEPORT 0 <Select> false PCW_DDR_PRIORITY_WRITEPORT_1 PCW DDR PRIORITY WRITEPORT 0 <Select> false PCW_DDR_PRIORITY_WRITEPORT_2 PCW DDR PRIORITY WRITEPORT 0 <Select> false PCW_DDR_PRIORITY_WRITEPORT_3 PCW DDR PRIORITY WRITEPORT 0 <Select> false PCW_DDR_PRIORITY_READPORT_0 PCW DDR PRIORITY READPORT 0 <Select> false PCW_DDR_PRIORITY_READPORT_1 PCW DDR PRIORITY READPORT 1 <Select> false PCW_DDR_PRIORITY_READPORT_2 PCW DDR PRIORITY READPORT 2 <Select> false PCW_DDR_PRIORITY_READPORT_3 PCW DDR PRIORITY READPORT 3 <Select> false PCW_DDR_PORT0_HPR_ENABLE PCW DDR PORT0 ENABLE HPR 0 false PCW_DDR_PORT1_HPR_ENABLE PCW DDR PORT1 ENABLE HPR 0 false PCW_DDR_PORT2_HPR_ENABLE PCW DDR PORT2 ENABLE HPR 0 false PCW_DDR_PORT3_HPR_ENABLE PCW DDR PORT3 ENABLE HPR 0 false PCW_DDR_HPRLPR_QUEUE_PARTITION PCW DDR HPRLPR QUEUE PARTITION HPR(0)/LPR(32) false PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL PCW DDR LPR TO CRITICAL PRIORITY LEVEL 2 false PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL PCW DDR HPR TO CRITICAL PRIORITY LEVEL 15 false PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL PCW DDR WRITE TO CRITICAL PRIORITY LEVEL 2 false PCW_NAND_PERIPHERAL_ENABLE PCW NAND PERIPHERAL ENABLE 0 PCW_NAND_NAND_IO PCW NAND NAND IO <Select> false PCW_NAND_GRP_D8_ENABLE 0 false PCW_NAND_GRP_D8_IO PCW NAND GRP D8 IO <Select> false PCW_NOR_PERIPHERAL_ENABLE PCW NOR PERIPHERAL ENABLE 0 PCW_NOR_NOR_IO PCW NOR NOR IO <Select> false PCW_NOR_GRP_A25_ENABLE PCW NOR GRP A25 IO 0 false PCW_NOR_GRP_A25_IO PCW NOR GRP CS0 IO <Select> false PCW_NOR_GRP_CS0_ENABLE 0 false PCW_NOR_GRP_CS0_IO PCW NOR GRP CS1 IO <Select> false PCW_NOR_GRP_SRAM_CS0_ENABLE PCW NOR GRP SRAM CS0 ENABLE 0 false PCW_NOR_GRP_SRAM_CS0_IO PCW NOR GRP SRAM CS1 IO <Select> false PCW_NOR_GRP_CS1_ENABLE 0 false PCW_NOR_GRP_CS1_IO PCW NOR GRP SRAM CS0 IO <Select> false PCW_NOR_GRP_SRAM_CS1_ENABLE PCW NOR GRP SRAM CS1 ENABLE 0 false PCW_NOR_GRP_SRAM_CS1_IO <Select> false PCW_NOR_GRP_SRAM_INT_ENABLE 0 false PCW_NOR_GRP_SRAM_INT_IO <Select> false PCW_QSPI_PERIPHERAL_ENABLE PCW QSPI PERIPHERAL ENABLE 0 PCW_QSPI_QSPI_IO PCW QSPI QSPI IO <Select> false PCW_QSPI_GRP_SINGLE_SS_ENABLE PCW QSPI GRP SINGLE SS ENABLE 0 false PCW_QSPI_GRP_SINGLE_SS_IO PCW QSPI GRP SINGLE SS IO <Select> false PCW_QSPI_GRP_SS1_ENABLE 0 false PCW_QSPI_GRP_SS1_IO PCW QSPI GRP SS1 IO <Select> false PCW_SINGLE_QSPI_DATA_MODE Single QSPI Data Mode <Select> false PCW_DUAL_STACK_QSPI_DATA_MODE Dual Stack QSPI Data Mode <Select> false PCW_DUAL_PARALLEL_QSPI_DATA_MODE Dual Parallel QSPI Data Mode <Select> false PCW_QSPI_GRP_IO1_ENABLE 0 false PCW_QSPI_GRP_IO1_IO PCW QSPI GRP IO1 IO <Select> false PCW_QSPI_GRP_FBCLK_ENABLE 0 false PCW_QSPI_GRP_FBCLK_IO PCW QSPI GRP FBCLK IO <Select> false PCW_QSPI_INTERNAL_HIGHADDRESS PCW QSPI INTERNAL HIGHADDRESS 0xFCFFFFFF PCW_ENET0_PERIPHERAL_ENABLE PCW ENET0 PERIPHERAL ENABLE 0 PCW_ENET0_ENET0_IO PCW ENET0 ENET0 IO <Select> false PCW_ENET0_GRP_MDIO_ENABLE 0 false PCW_ENET0_GRP_MDIO_IO PCW ENET0 GRP MDIO IO <Select> false PCW_ENET_RESET_ENABLE 0 false PCW_ENET_RESET_SELECT <Select> false PCW_ENET0_RESET_ENABLE 0 false PCW_ENET0_RESET_IO <Select> false PCW_ENET1_PERIPHERAL_ENABLE PCW ENET1 PERIPHERAL ENABLE 0 PCW_ENET1_ENET1_IO PCW ENET1 ENET1 IO <Select> false PCW_ENET1_GRP_MDIO_ENABLE 0 false PCW_ENET1_GRP_MDIO_IO PCW ENET1 GRP MDIO IO <Select> false PCW_ENET1_RESET_ENABLE 0 false PCW_ENET1_RESET_IO <Select> false PCW_SD0_PERIPHERAL_ENABLE PCW SD0 PERIPHERAL ENABLE 0 PCW_SD0_SD0_IO PCW SD0 SD0 IO <Select> false PCW_SD0_GRP_CD_ENABLE 0 false PCW_SD0_GRP_CD_IO PCW SD0 GRP CD IO <Select> false PCW_SD0_GRP_WP_ENABLE 0 false PCW_SD0_GRP_WP_IO PCW SD0 GRP WP IO <Select> false PCW_SD0_GRP_POW_ENABLE 0 false PCW_SD0_GRP_POW_IO PCW SD0 GRP POW IO <Select> false PCW_SD1_PERIPHERAL_ENABLE PCW SD1 PERIPHERAL ENABLE 0 PCW_SD1_SD1_IO PCW SD1 SD1 IO <Select> false PCW_SD1_GRP_CD_ENABLE 0 false PCW_SD1_GRP_CD_IO PCW SD1 GRP CD IO <Select> false PCW_SD1_GRP_WP_ENABLE 0 false PCW_SD1_GRP_WP_IO PCW SD1 GRP WP IO <Select> false PCW_SD1_GRP_POW_ENABLE 0 false PCW_SD1_GRP_POW_IO PCW SD1 GRP POW IO <Select> false PCW_UART0_PERIPHERAL_ENABLE PCW UART0 PERIPHERAL ENABLE 0 PCW_UART0_UART0_IO PCW UART0 UART0 IO <Select> false PCW_UART0_GRP_FULL_ENABLE 0 false PCW_UART0_GRP_FULL_IO <Select> false PCW_UART1_PERIPHERAL_ENABLE PCW UART1 PERIPHERAL ENABLE 1 PCW_UART1_UART1_IO PCW UART1 UART1 IO MIO 44 .. 45 PCW_UART1_GRP_FULL_ENABLE 0 PCW_UART1_GRP_FULL_IO <Select> false PCW_SPI0_PERIPHERAL_ENABLE PCW SPI0 PERIPHERAL ENABLE 0 PCW_SPI0_SPI0_IO PCW SPI0 SPI0 IO <Select> false PCW_SPI0_GRP_SS0_ENABLE 0 false PCW_SPI0_GRP_SS0_IO PCW SPI0 GRP SS0 IO <Select> false PCW_SPI0_GRP_SS1_ENABLE 0 false PCW_SPI0_GRP_SS1_IO PCW SPI0 GRP SS1 IO <Select> false PCW_SPI0_GRP_SS2_ENABLE 0 false PCW_SPI0_GRP_SS2_IO PCW SPI0 GRP SS2 IO <Select> false PCW_SPI1_PERIPHERAL_ENABLE PCW SPI1 PERIPHERAL ENABLE 0 PCW_SPI1_SPI1_IO PCW SPI1 SPI1 IO <Select> false PCW_SPI1_GRP_SS0_ENABLE 0 false PCW_SPI1_GRP_SS0_IO PCW SPI1 GRP SS0 IO <Select> false PCW_SPI1_GRP_SS1_ENABLE 0 false PCW_SPI1_GRP_SS1_IO PCW SPI1 GRP SS1 IO <Select> false PCW_SPI1_GRP_SS2_ENABLE 0 false PCW_SPI1_GRP_SS2_IO PCW SPI1 GRP SS2 IO <Select> false PCW_CAN0_PERIPHERAL_ENABLE PCW CAN0 PERIPHERAL ENABLE 0 PCW_CAN0_CAN0_IO PCW CAN0 CAN0 IO <Select> false PCW_CAN0_GRP_CLK_ENABLE 0 false PCW_CAN0_GRP_CLK_IO PCW CAN0 GRP CLK IO <Select> false PCW_CAN1_PERIPHERAL_ENABLE PCW CAN1 PERIPHERAL ENABLE 0 PCW_CAN1_CAN1_IO PCW CAN1 CAN1 IO <Select> false PCW_CAN1_GRP_CLK_ENABLE 0 false PCW_CAN1_GRP_CLK_IO PCW CAN1 GRP CLK IO <Select> false PCW_TRACE_PERIPHERAL_ENABLE PCW TRACE PERIPHERAL ENABLE 0 PCW_TRACE_TRACE_IO PCW TRACE TRACE IO <Select> false PCW_TRACE_GRP_2BIT_ENABLE 0 false PCW_TRACE_GRP_2BIT_IO PCW TRACE GRP 2BIT IO <Select> false PCW_TRACE_GRP_4BIT_ENABLE 0 false PCW_TRACE_GRP_4BIT_IO PCW TRACE GRP 4BIT IO <Select> false PCW_TRACE_GRP_8BIT_ENABLE 0 false PCW_TRACE_GRP_8BIT_IO PCW TRACE GRP 8BIT IO <Select> false PCW_TRACE_GRP_16BIT_ENABLE 0 false PCW_TRACE_GRP_16BIT_IO PCW TRACE GRP 16BIT IO <Select> false PCW_TRACE_GRP_32BIT_ENABLE 0 false PCW_TRACE_GRP_32BIT_IO PCW TRACE GRP 32BIT IO <Select> false PCW_TRACE_INTERNAL_WIDTH PCW TRACE INTERNAL WIDTH 2 PCW_WDT_PERIPHERAL_ENABLE PCW WDT PERIPHERAL ENABLE 0 PCW_WDT_WDT_IO PCW WDT WDT IO <Select> false PCW_TTC0_PERIPHERAL_ENABLE PCW TTC0 PERIPHERAL ENABLE 0 PCW_TTC0_TTC0_IO PCW TTC0 TTC0 IO <Select> false PCW_TTC1_PERIPHERAL_ENABLE PCW TTC1 PERIPHERAL ENABLE 0 PCW_TTC1_TTC1_IO PCW TTC1 TTC1 IO <Select> false PCW_PJTAG_PERIPHERAL_ENABLE PCW PJTAG PERIPHERAL ENABLE 0 PCW_PJTAG_PJTAG_IO PCW PJTAG PJTAG IO <Select> false PCW_USB0_PERIPHERAL_ENABLE PCW USB0 PERIPHERAL ENABLE 0 PCW_USB0_USB0_IO PCW USB0 USB0 IO <Select> false PCW_USB_RESET_ENABLE 0 false PCW_USB_RESET_SELECT <Select> false PCW_USB0_RESET_ENABLE 0 false PCW_USB0_RESET_IO <Select> false PCW_USB1_PERIPHERAL_ENABLE PCW USB1 PERIPHERAL ENABLE 0 PCW_USB1_USB1_IO PCW USB1 USB1 IO <Select> false PCW_USB1_RESET_ENABLE 0 false PCW_USB1_RESET_IO <Select> false PCW_I2C0_PERIPHERAL_ENABLE PCW I2C0 PERIPHERAL ENABLE 0 PCW_I2C0_I2C0_IO PCW I2C0 I2C0 IO <Select> false PCW_I2C0_GRP_INT_ENABLE 0 false PCW_I2C0_GRP_INT_IO PCW I2C0 GRP INT IO <Select> false PCW_I2C0_RESET_ENABLE 0 false PCW_I2C0_RESET_IO <Select> false PCW_I2C1_PERIPHERAL_ENABLE PCW I2C1 PERIPHERAL ENABLE 0 PCW_I2C1_I2C1_IO PCW I2C1 I2C1 IO <Select> false PCW_I2C1_GRP_INT_ENABLE 0 false PCW_I2C1_GRP_INT_IO PCW I2C1 GRP INT IO <Select> false PCW_I2C_RESET_ENABLE 0 false PCW_I2C_RESET_SELECT <Select> false PCW_I2C1_RESET_ENABLE 0 false PCW_I2C1_RESET_IO <Select> false PCW_GPIO_PERIPHERAL_ENABLE PCW GPIO PERIPHERAL ENABLE 0 PCW_GPIO_MIO_GPIO_ENABLE 0 PCW_GPIO_MIO_GPIO_IO PCW GPIO MIO GPIO IO <Select> false PCW_GPIO_EMIO_GPIO_ENABLE PCW GPIO EMIO GPIO ENABLE 0 PCW_GPIO_EMIO_GPIO_IO PCW GPIO EMIO GPIO IO <Select> false PCW_APU_CLK_RATIO_ENABLE PCW APU CLK RATIO ENABLE 6:2:1 PCW_ENET0_PERIPHERAL_FREQMHZ PCW ENET0 PERIPHERAL FREQMHZ 1000 Mbps false PCW_ENET1_PERIPHERAL_FREQMHZ PCW ENET1 PERIPHERAL FREQMHZ 1000 Mbps false PCW_CPU_PERIPHERAL_CLKSRC PCW CPU PERIPHERAL CLKSRC ARM PLL PCW_DDR_PERIPHERAL_CLKSRC PCW DDR PERIPHERAL CLKSRC DDR PLL PCW_SMC_PERIPHERAL_CLKSRC PCW SMC PERIPHERAL CLKSRC IO PLL PCW_QSPI_PERIPHERAL_CLKSRC PCW QSPI PERIPHERAL CLKSRC IO PLL PCW_SDIO_PERIPHERAL_CLKSRC PCW SDIO PERIPHERAL CLKSRC IO PLL PCW_UART_PERIPHERAL_CLKSRC PCW UART PERIPHERAL CLKSRC IO PLL PCW_SPI_PERIPHERAL_CLKSRC PCW SPI PERIPHERAL CLKSRC IO PLL PCW_CAN_PERIPHERAL_CLKSRC PCW CAN PERIPHERAL CLKSRC IO PLL PCW_FCLK0_PERIPHERAL_CLKSRC PCW FCLK0 PERIPHERAL CLKSRC IO PLL PCW_FCLK1_PERIPHERAL_CLKSRC PCW FCLK1 PERIPHERAL CLKSRC IO PLL PCW_FCLK2_PERIPHERAL_CLKSRC PCW FCLK2 PERIPHERAL CLKSRC IO PLL PCW_FCLK3_PERIPHERAL_CLKSRC PCW FCLK3 PERIPHERAL CLKSRC IO PLL PCW_ENET0_PERIPHERAL_CLKSRC PCW ENET0 PERIPHERAL CLKSRC IO PLL PCW_ENET1_PERIPHERAL_CLKSRC PCW ENET1 PERIPHERAL CLKSRC IO PLL PCW_CAN0_PERIPHERAL_CLKSRC PCW CAN0 PERIPHERAL CLKSRC External PCW_CAN1_PERIPHERAL_CLKSRC PCW CAN1 PERIPHERAL CLKSRC External PCW_TPIU_PERIPHERAL_CLKSRC PCW TPIU PERIPHERAL CLKSRC External PCW_TTC0_CLK0_PERIPHERAL_CLKSRC PCW TTC0 CLK0 PERIPHERAL CLKSRC CPU_1X PCW_TTC0_CLK1_PERIPHERAL_CLKSRC PCW TTC0 CLK1 PERIPHERAL CLKSRC CPU_1X PCW_TTC0_CLK2_PERIPHERAL_CLKSRC PCW TTC0 CLK2 PERIPHERAL CLKSRC CPU_1X PCW_TTC1_CLK0_PERIPHERAL_CLKSRC PCW TTC1 CLK0 PERIPHERAL CLKSRC CPU_1X PCW_TTC1_CLK1_PERIPHERAL_CLKSRC PCW TTC1 CLK1 PERIPHERAL CLKSRC CPU_1X PCW_TTC1_CLK2_PERIPHERAL_CLKSRC PCW TTC1 CLK2 PERIPHERAL CLKSRC CPU_1X PCW_WDT_PERIPHERAL_CLKSRC PCW WDT PERIPHERAL CLKSRC CPU_1X PCW_DCI_PERIPHERAL_CLKSRC PCW DCI PERIPHERAL CLKSRC DDR PLL PCW_PCAP_PERIPHERAL_CLKSRC PCW PCAP PERIPHERAL CLKSRC IO PLL PCW_USB_RESET_POLARITY PCW USB RESET POLARITY Active Low PCW_ENET_RESET_POLARITY PCW USB RESET POLARITY Active Low PCW_I2C_RESET_POLARITY PCW USB RESET POLARITY Active Low PCW_MIO_0_PULLUP PCW MIO 0 PULLUP <Select> false PCW_MIO_0_IOTYPE PCW MIO 0 IOTYPE <Select> false PCW_MIO_0_DIRECTION PCW MIO 0 DIRECTION <Select> false PCW_MIO_0_SLEW PCW MIO 0 SLEW <Select> false PCW_MIO_1_PULLUP PCW MIO 1 PULLUP <Select> false PCW_MIO_1_IOTYPE PCW MIO 1 IOTYPE <Select> false PCW_MIO_1_DIRECTION PCW MIO 1 DIRECTION <Select> false PCW_MIO_1_SLEW PCW MIO 1 SLEW <Select> false PCW_MIO_2_PULLUP PCW MIO 2 PULLUP <Select> false PCW_MIO_2_IOTYPE PCW MIO 2 IOTYPE <Select> false PCW_MIO_2_DIRECTION PCW MIO 2 DIRECTION <Select> false PCW_MIO_2_SLEW PCW MIO 2 SLEW <Select> false PCW_MIO_3_PULLUP PCW MIO 3 PULLUP <Select> false PCW_MIO_3_IOTYPE PCW MIO 3 IOTYPE <Select> false PCW_MIO_3_DIRECTION PCW MIO 3 DIRECTION <Select> false PCW_MIO_3_SLEW PCW MIO 3 SLEW <Select> false PCW_MIO_4_PULLUP PCW MIO 4 PULLUP <Select> false PCW_MIO_4_IOTYPE PCW MIO 4 IOTYPE <Select> false PCW_MIO_4_DIRECTION PCW MIO 4 DIRECTION <Select> false PCW_MIO_4_SLEW PCW MIO 4 SLEW <Select> false PCW_MIO_5_PULLUP PCW MIO 5 PULLUP <Select> false PCW_MIO_5_IOTYPE PCW MIO 5 IOTYPE <Select> false PCW_MIO_5_DIRECTION PCW MIO 5 DIRECTION <Select> false PCW_MIO_5_SLEW PCW MIO 5 SLEW <Select> false PCW_MIO_6_PULLUP PCW MIO 6 PULLUP <Select> false PCW_MIO_6_IOTYPE PCW MIO 6 IOTYPE <Select> false PCW_MIO_6_DIRECTION PCW MIO 6 DIRECTION <Select> false PCW_MIO_6_SLEW PCW MIO 6 SLEW <Select> false PCW_MIO_7_PULLUP PCW MIO 7 PULLUP <Select> false PCW_MIO_7_IOTYPE PCW MIO 7 IOTYPE <Select> false PCW_MIO_7_DIRECTION PCW MIO 7 DIRECTION <Select> false PCW_MIO_7_SLEW PCW MIO 7 SLEW <Select> false PCW_MIO_8_PULLUP PCW MIO 8 PULLUP <Select> false PCW_MIO_8_IOTYPE PCW MIO 8 IOTYPE <Select> false PCW_MIO_8_DIRECTION PCW MIO 8 DIRECTION <Select> false PCW_MIO_8_SLEW PCW MIO 8 SLEW <Select> false PCW_MIO_9_PULLUP PCW MIO 9 PULLUP <Select> false PCW_MIO_9_IOTYPE PCW MIO 9 IOTYPE <Select> false PCW_MIO_9_DIRECTION PCW MIO 9 DIRECTION <Select> false PCW_MIO_9_SLEW PCW MIO 9 SLEW <Select> false PCW_MIO_10_PULLUP PCW MIO 10 PULLUP <Select> false PCW_MIO_10_IOTYPE PCW MIO 10 IOTYPE <Select> false PCW_MIO_10_DIRECTION PCW MIO 10 DIRECTION <Select> false PCW_MIO_10_SLEW PCW MIO 10 SLEW <Select> false PCW_MIO_11_PULLUP PCW MIO 11 PULLUP <Select> false PCW_MIO_11_IOTYPE PCW MIO 11 IOTYPE <Select> false PCW_MIO_11_DIRECTION PCW MIO 11 DIRECTION <Select> false PCW_MIO_11_SLEW PCW MIO 11 SLEW <Select> false PCW_MIO_12_PULLUP PCW MIO 12 PULLUP <Select> false PCW_MIO_12_IOTYPE PCW MIO 12 IOTYPE <Select> false PCW_MIO_12_DIRECTION PCW MIO 12 DIRECTION <Select> false PCW_MIO_12_SLEW PCW MIO 12 SLEW <Select> false PCW_MIO_13_PULLUP PCW MIO 13 PULLUP <Select> false PCW_MIO_13_IOTYPE PCW MIO 13 IOTYPE <Select> false PCW_MIO_13_DIRECTION PCW MIO 13 DIRECTION <Select> false PCW_MIO_13_SLEW PCW MIO 13 SLEW <Select> false PCW_MIO_14_PULLUP PCW MIO 14 PULLUP <Select> false PCW_MIO_14_IOTYPE PCW MIO 14 IOTYPE <Select> false PCW_MIO_14_DIRECTION PCW MIO 14 DIRECTION <Select> false PCW_MIO_14_SLEW PCW MIO 14 SLEW <Select> false PCW_MIO_15_PULLUP PCW MIO 15 PULLUP <Select> false PCW_MIO_15_IOTYPE PCW MIO 15 IOTYPE <Select> false PCW_MIO_15_DIRECTION PCW MIO 15 DIRECTION <Select> false PCW_MIO_15_SLEW PCW MIO 15 SLEW <Select> false PCW_MIO_16_PULLUP PCW MIO 16 PULLUP <Select> false PCW_MIO_16_IOTYPE PCW MIO 16 IOTYPE <Select> false PCW_MIO_16_DIRECTION PCW MIO 16 DIRECTION <Select> false PCW_MIO_16_SLEW PCW MIO 16 SLEW <Select> false PCW_MIO_17_PULLUP PCW MIO 17 PULLUP <Select> false PCW_MIO_17_IOTYPE PCW MIO 17 IOTYPE <Select> false PCW_MIO_17_DIRECTION PCW MIO 17 DIRECTION <Select> false PCW_MIO_17_SLEW PCW MIO 17 SLEW <Select> false PCW_MIO_18_PULLUP PCW MIO 18 PULLUP <Select> false PCW_MIO_18_IOTYPE PCW MIO 18 IOTYPE <Select> false PCW_MIO_18_DIRECTION PCW MIO 18 DIRECTION <Select> false PCW_MIO_18_SLEW PCW MIO 18 SLEW <Select> false PCW_MIO_19_PULLUP PCW MIO 19 PULLUP <Select> false PCW_MIO_19_IOTYPE PCW MIO 19 IOTYPE <Select> false PCW_MIO_19_DIRECTION PCW MIO 19 DIRECTION <Select> false PCW_MIO_19_SLEW PCW MIO 19 SLEW <Select> false PCW_MIO_20_PULLUP PCW MIO 20 PULLUP <Select> false PCW_MIO_20_IOTYPE PCW MIO 20 IOTYPE <Select> false PCW_MIO_20_DIRECTION PCW MIO 20 DIRECTION <Select> false PCW_MIO_20_SLEW PCW MIO 20 SLEW <Select> false PCW_MIO_21_PULLUP PCW MIO 21 PULLUP <Select> false PCW_MIO_21_IOTYPE PCW MIO 21 IOTYPE <Select> false PCW_MIO_21_DIRECTION PCW MIO 21 DIRECTION <Select> false PCW_MIO_21_SLEW PCW MIO 21 SLEW <Select> false PCW_MIO_22_PULLUP PCW MIO 22 PULLUP <Select> false PCW_MIO_22_IOTYPE PCW MIO 22 IOTYPE <Select> false PCW_MIO_22_DIRECTION PCW MIO 22 DIRECTION <Select> false PCW_MIO_22_SLEW PCW MIO 22 SLEW <Select> false PCW_MIO_23_PULLUP PCW MIO 23 PULLUP <Select> false PCW_MIO_23_IOTYPE PCW MIO 23 IOTYPE <Select> false PCW_MIO_23_DIRECTION PCW MIO 23 DIRECTION <Select> false PCW_MIO_23_SLEW PCW MIO 23 SLEW <Select> false PCW_MIO_24_PULLUP PCW MIO 24 PULLUP <Select> false PCW_MIO_24_IOTYPE PCW MIO 24 IOTYPE <Select> false PCW_MIO_24_DIRECTION PCW MIO 24 DIRECTION <Select> false PCW_MIO_24_SLEW PCW MIO 24 SLEW <Select> false PCW_MIO_25_PULLUP PCW MIO 25 PULLUP <Select> false PCW_MIO_25_IOTYPE PCW MIO 25 IOTYPE <Select> false PCW_MIO_25_DIRECTION PCW MIO 25 DIRECTION <Select> false PCW_MIO_25_SLEW PCW MIO 25 SLEW <Select> false PCW_MIO_26_PULLUP PCW MIO 26 PULLUP <Select> false PCW_MIO_26_IOTYPE PCW MIO 26 IOTYPE <Select> false PCW_MIO_26_DIRECTION PCW MIO 26 DIRECTION <Select> false PCW_MIO_26_SLEW PCW MIO 26 SLEW <Select> false PCW_MIO_27_PULLUP PCW MIO 27 PULLUP <Select> false PCW_MIO_27_IOTYPE PCW MIO 27 IOTYPE <Select> false PCW_MIO_27_DIRECTION PCW MIO 27 DIRECTION <Select> false PCW_MIO_27_SLEW PCW MIO 27 SLEW <Select> false PCW_MIO_28_PULLUP PCW MIO 28 PULLUP <Select> false PCW_MIO_28_IOTYPE PCW MIO 28 IOTYPE <Select> false PCW_MIO_28_DIRECTION PCW MIO 28 DIRECTION <Select> false PCW_MIO_28_SLEW PCW MIO 28 SLEW <Select> false PCW_MIO_29_PULLUP PCW MIO 29 PULLUP <Select> false PCW_MIO_29_IOTYPE PCW MIO 29 IOTYPE <Select> false PCW_MIO_29_DIRECTION PCW MIO 29 DIRECTION <Select> false PCW_MIO_29_SLEW PCW MIO 29 SLEW <Select> false PCW_MIO_30_PULLUP PCW MIO 30 PULLUP <Select> false PCW_MIO_30_IOTYPE PCW MIO 30 IOTYPE <Select> false PCW_MIO_30_DIRECTION PCW MIO 30 DIRECTION <Select> false PCW_MIO_30_SLEW PCW MIO 30 SLEW <Select> false PCW_MIO_31_PULLUP PCW MIO 31 PULLUP <Select> false PCW_MIO_31_IOTYPE PCW MIO 31 IOTYPE <Select> false PCW_MIO_31_DIRECTION PCW MIO 31 DIRECTION <Select> false PCW_MIO_31_SLEW PCW MIO 31 SLEW <Select> false PCW_MIO_32_PULLUP PCW MIO 32 PULLUP <Select> false PCW_MIO_32_IOTYPE PCW MIO 32 IOTYPE <Select> false PCW_MIO_32_DIRECTION PCW MIO 32 DIRECTION <Select> false PCW_MIO_32_SLEW PCW MIO 32 SLEW <Select> false PCW_MIO_33_PULLUP PCW MIO 33 PULLUP <Select> false PCW_MIO_33_IOTYPE PCW MIO 33 IOTYPE <Select> false PCW_MIO_33_DIRECTION PCW MIO 33 DIRECTION <Select> false PCW_MIO_33_SLEW PCW MIO 33 SLEW <Select> false PCW_MIO_34_PULLUP PCW MIO 34 PULLUP <Select> false PCW_MIO_34_IOTYPE PCW MIO 34 IOTYPE <Select> false PCW_MIO_34_DIRECTION PCW MIO 34 DIRECTION <Select> false PCW_MIO_34_SLEW PCW MIO 34 SLEW <Select> false PCW_MIO_35_PULLUP PCW MIO 35 PULLUP <Select> false PCW_MIO_35_IOTYPE PCW MIO 35 IOTYPE <Select> false PCW_MIO_35_DIRECTION PCW MIO 35 DIRECTION <Select> false PCW_MIO_35_SLEW PCW MIO 35 SLEW <Select> false PCW_MIO_36_PULLUP PCW MIO 36 PULLUP <Select> false PCW_MIO_36_IOTYPE PCW MIO 36 IOTYPE <Select> false PCW_MIO_36_DIRECTION PCW MIO 36 DIRECTION <Select> false PCW_MIO_36_SLEW PCW MIO 36 SLEW <Select> false PCW_MIO_37_PULLUP PCW MIO 37 PULLUP <Select> false PCW_MIO_37_IOTYPE PCW MIO 37 IOTYPE <Select> false PCW_MIO_37_DIRECTION PCW MIO 37 DIRECTION <Select> false PCW_MIO_37_SLEW PCW MIO 37 SLEW <Select> false PCW_MIO_38_PULLUP PCW MIO 38 PULLUP <Select> false PCW_MIO_38_IOTYPE PCW MIO 38 IOTYPE <Select> false PCW_MIO_38_DIRECTION PCW MIO 38 DIRECTION <Select> false PCW_MIO_38_SLEW PCW MIO 38 SLEW <Select> false PCW_MIO_39_PULLUP PCW MIO 39 PULLUP <Select> false PCW_MIO_39_IOTYPE PCW MIO 39 IOTYPE <Select> false PCW_MIO_39_DIRECTION PCW MIO 39 DIRECTION <Select> false PCW_MIO_39_SLEW PCW MIO 39 SLEW <Select> false PCW_MIO_40_PULLUP PCW MIO 40 PULLUP <Select> false PCW_MIO_40_IOTYPE PCW MIO 40 IOTYPE <Select> false PCW_MIO_40_DIRECTION PCW MIO 40 DIRECTION <Select> false PCW_MIO_40_SLEW PCW MIO 40 SLEW <Select> false PCW_MIO_41_PULLUP PCW MIO 41 PULLUP <Select> false PCW_MIO_41_IOTYPE PCW MIO 41 IOTYPE <Select> false PCW_MIO_41_DIRECTION PCW MIO 41 DIRECTION <Select> false PCW_MIO_41_SLEW PCW MIO 41 SLEW <Select> false PCW_MIO_42_PULLUP PCW MIO 42 PULLUP <Select> false PCW_MIO_42_IOTYPE PCW MIO 42 IOTYPE <Select> false PCW_MIO_42_DIRECTION PCW MIO 42 DIRECTION <Select> false PCW_MIO_42_SLEW PCW MIO 42 SLEW <Select> false PCW_MIO_43_PULLUP PCW MIO 43 PULLUP <Select> false PCW_MIO_43_IOTYPE PCW MIO 43 IOTYPE <Select> false PCW_MIO_43_DIRECTION PCW MIO 43 DIRECTION <Select> false PCW_MIO_43_SLEW PCW MIO 43 SLEW <Select> false PCW_MIO_44_PULLUP PCW MIO 44 PULLUP enabled PCW_MIO_44_IOTYPE PCW MIO 44 IOTYPE LVCMOS 3.3V PCW_MIO_44_DIRECTION PCW MIO 44 DIRECTION out false PCW_MIO_44_SLEW PCW MIO 44 SLEW slow PCW_MIO_45_PULLUP PCW MIO 45 PULLUP enabled PCW_MIO_45_IOTYPE PCW MIO 45 IOTYPE LVCMOS 3.3V PCW_MIO_45_DIRECTION PCW MIO 45 DIRECTION in false PCW_MIO_45_SLEW PCW MIO 45 SLEW slow PCW_MIO_46_PULLUP PCW MIO 46 PULLUP <Select> false PCW_MIO_46_IOTYPE PCW MIO 46 IOTYPE <Select> false PCW_MIO_46_DIRECTION PCW MIO 46 DIRECTION <Select> false PCW_MIO_46_SLEW PCW MIO 46 SLEW <Select> false PCW_MIO_47_PULLUP PCW MIO 47 PULLUP <Select> false PCW_MIO_47_IOTYPE PCW MIO 47 IOTYPE <Select> false PCW_MIO_47_DIRECTION PCW MIO 47 DIRECTION <Select> false PCW_MIO_47_SLEW PCW MIO 47 SLEW <Select> false PCW_MIO_48_PULLUP PCW MIO 48 PULLUP <Select> false PCW_MIO_48_IOTYPE PCW MIO 48 IOTYPE <Select> false PCW_MIO_48_DIRECTION PCW MIO 48 DIRECTION <Select> false PCW_MIO_48_SLEW PCW MIO 48 SLEW <Select> false PCW_MIO_49_PULLUP PCW MIO 49 PULLUP <Select> false PCW_MIO_49_IOTYPE PCW MIO 49 IOTYPE <Select> false PCW_MIO_49_DIRECTION PCW MIO 49 DIRECTION <Select> false PCW_MIO_49_SLEW PCW MIO 49 SLEW <Select> false PCW_MIO_50_PULLUP PCW MIO 50 PULLUP <Select> false PCW_MIO_50_IOTYPE PCW MIO 50 IOTYPE <Select> false PCW_MIO_50_DIRECTION PCW MIO 50 DIRECTION <Select> false PCW_MIO_50_SLEW PCW MIO 50 SLEW <Select> false PCW_MIO_51_PULLUP PCW MIO 51 PULLUP <Select> false PCW_MIO_51_IOTYPE PCW MIO 51 IOTYPE <Select> false PCW_MIO_51_DIRECTION PCW MIO 51 DIRECTION <Select> false PCW_MIO_51_SLEW PCW MIO 51 SLEW <Select> false PCW_MIO_52_PULLUP PCW MIO 52 PULLUP <Select> false PCW_MIO_52_IOTYPE PCW MIO 52 IOTYPE <Select> false PCW_MIO_52_DIRECTION PCW MIO 52 DIRECTION <Select> false PCW_MIO_52_SLEW PCW MIO 52 SLEW <Select> false PCW_MIO_53_PULLUP PCW MIO 53 PULLUP <Select> false PCW_MIO_53_IOTYPE PCW MIO 53 IOTYPE <Select> false PCW_MIO_53_DIRECTION PCW MIO 53 DIRECTION <Select> false PCW_MIO_53_SLEW PCW MIO 53 SLEW <Select> false preset preset None PCW_UIPARAM_GENERATE_SUMMARY PCW UIPARAM GENERATE SUMMARY NA PCW_MIO_TREE_PERIPHERALS PCW MIO TREE PERIPHERALS unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#un assigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned PCW_MIO_TREE_SIGNALS PCW MIO TREE SIGNALS unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned #unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned PCW_PS7_SI_REV PCW PS7 SI REV PRODUCTION PCW_FPGA_FCLK0_ENABLE PCW FPGA FCLK0 ENABLE 1 true PCW_FPGA_FCLK1_ENABLE PCW FPGA FCLK1 ENABLE 0 false PCW_FPGA_FCLK2_ENABLE PCW FPGA FCLK2 ENABLE 0 false PCW_FPGA_FCLK3_ENABLE PCW FPGA FCLK3 ENABLE 0 false PCW_NOR_SRAM_CS0_T_TR PCW NOR SRAM CS0 T TR 1 PCW_NOR_SRAM_CS0_T_PC PCW NOR SRAM CS0 T PC 1 PCW_NOR_SRAM_CS0_T_WP PCW NOR SRAM CS0 T WP 1 PCW_NOR_SRAM_CS0_T_CEOE PCW NOR SRAM CS0 T CEOE 1 PCW_NOR_SRAM_CS0_T_WC PCW NOR SRAM CS0 T WC 11 PCW_NOR_SRAM_CS0_T_RC PCW NOR SRAM CS0 T RC 11 PCW_NOR_SRAM_CS0_WE_TIME PCW NOR SRAM CS0 WE TIME 0 PCW_NOR_SRAM_CS1_T_TR PCW NOR SRAM CS1 T TR 1 PCW_NOR_SRAM_CS1_T_PC PCW NOR SRAM CS1 T PC 1 PCW_NOR_SRAM_CS1_T_WP PCW NOR SRAM CS1 T WP 1 PCW_NOR_SRAM_CS1_T_CEOE PCW NOR SRAM CS1 T CEOE 1 PCW_NOR_SRAM_CS1_T_WC PCW NOR SRAM CS1 T WC 11 PCW_NOR_SRAM_CS1_T_RC PCW NOR SRAM CS1 T RC 11 PCW_NOR_SRAM_CS1_WE_TIME PCW NOR SRAM CS1 WE TIME 0 PCW_NOR_CS0_T_TR PCW NOR CS0 T TR 1 PCW_NOR_CS0_T_PC PCW NOR CS0 T PC 1 PCW_NOR_CS0_T_WP PCW NOR CS0 T WP 1 PCW_NOR_CS0_T_CEOE PCW NOR CS0 T CEOE 1 PCW_NOR_CS0_T_WC PCW NOR CS0 T WC 11 PCW_NOR_CS0_T_RC PCW NOR CS0 T RC 11 PCW_NOR_CS0_WE_TIME PCW NOR CS0 WE TIME 0 PCW_NOR_CS1_T_TR PCW NOR CS1 T TR 1 PCW_NOR_CS1_T_PC PCW NOR CS1 T PC 1 PCW_NOR_CS1_T_WP PCW NOR CS1 T WP 1 PCW_NOR_CS1_T_CEOE PCW NOR CS1 T CEOE 1 PCW_NOR_CS1_T_WC PCW NOR CS1 T WC 11 PCW_NOR_CS1_T_RC PCW NOR CS1 T RC 11 PCW_NOR_CS1_WE_TIME PCW NOR CS1 WE TIME 0 PCW_NAND_CYCLES_T_RR PCW NAND CYCLES T RR 1 PCW_NAND_CYCLES_T_AR PCW NAND CYCLES T AR 1 PCW_NAND_CYCLES_T_CLR PCW NAND CYCLES T CLR 1 PCW_NAND_CYCLES_T_WP PCW NAND CYCLES T WP 1 PCW_NAND_CYCLES_T_REA PCW NAND CYCLES T REA 1 PCW_NAND_CYCLES_T_WC PCW NAND CYCLES T WC 11 PCW_NAND_CYCLES_T_RC PCW NAND CYCLES T RC 11 PCW_SMC_CYCLE_T0 PCW SMC CYCLE T0 NA PCW_SMC_CYCLE_T1 PCW SMC CYCLE T1 NA PCW_SMC_CYCLE_T2 PCW SMC CYCLE T2 NA PCW_SMC_CYCLE_T3 PCW SMC CYCLE T3 NA PCW_SMC_CYCLE_T4 PCW SMC CYCLE T4 NA PCW_SMC_CYCLE_T5 PCW SMC CYCLE T5 NA PCW_SMC_CYCLE_T6 PCW SMC CYCLE T6 NA PCW_PACKAGE_NAME PCW PACKAGE NAME clg400 PCW_PLL_BYPASSMODE_ENABLE PCW PLL BYPASSMODE ENABLE 0 Component_Name zynqps ZYNQ7 Processing System remote_port_c_v4 remote_port_sc_v4 xtlm 6 true 2021.2