xilinx.com display_processing_system7 fixedio_rtl 1.0 MIO Multiplexed IO optional 54 inout optional 54 inout PS_SRSTB Debug system reset optional 1 inout optional 1 inout PS_CLK System reference clock optional 1 inout optional 1 inout PS_PORB Power on reset optional 1 inout optional 1 inout DDR_VRN DCI voltage reference. Connect DDR_VRN to a resister to VCC_DDR optional 1 inout optional 1 inout DDR_VRP DCI voltage reference. Connect DDR_VRP to a resistor to GND optional 1 inout optional 1 inout