[project]
name            = testproject
version         = 0.1
out_dir         = OUT
build_dir       = BUILD

[target:default]
family          = spartan6
device          = xc6slx9
package         = tqg144
speedgrade      = -2
toolchain       = ISE

[sources:default]
target          = default
toplevel        = toplevel
src_vhdl        = RTL/toplevel.vhd
src_verilog     = 
src_sysverilog  =