[project]
name                = zynq7000_project
version             = 0.1
out_dir             = OUT
build_dir           = BUILD

[server]
hostname            = localhost
port                = 2020
privkey             = /home/joppe/.ssh/id_rsa
pubkey              = /home/joppe/.ssh/id_rsa.pub

# ======================================
# BASIC FPGA WORKFLOW
# ======================================

# ######################################
# ISE IP block generation
[target.ip]
toolchain           = VIVADO_IP

# Toolchain settings
family              = zynq
device              = xc7z010
package             = clg400
speedgrade          = -2

# Fileset
files_tcl           = IP/zynqps.tcl IP/rst_gen.tcl
# Note: IP file names must be the same as the component name in the tcl file!

# ######################################

# ######################################
# Basic synthesis
[target.synth]
toolchain           = VIVADO

# Toolchain settings
family              = zynq
device              = xc7z010
package             = clg400
speedgrade          = -2
toplevel            = toplevel
# Created netlist toplevel
netlist_top         = toplevel.heartbeat_i heartbeat
# toplevel and name to give to exported netlist
synth_opts          = -flatten_hierarchy none -keep_equivalent_registers
#opt_opts           =
#place_opts         =
#route_opts         =

# Fileset
files_vhdl          = RTL/heartbeat.vhd RTL/toplevel.vhd
#files_verilog      =
#files_sysverilog   =
files_con           = CON/toplevel.xdc
files_xci           = OUT/ip/rst_gen/rst_gen.xci OUT/ip/zynqps/zynqps.xci
# ######################################

# ######################################
# Behavioural simulation
[target.sim]
toolchain           = xsim

# Toolchain settings
toplevel            = tb_heartbeat
vcdlevels           = 20
runtime             = all
#xelab_opts         = 

# Fileset
files_vhdl          = RTL/heartbeat.vhd
                      SIM/tb_heartbeat.vhd
#files_verilog      =
#files_sysverilog   =
#files_xci          = 
# ######################################

# ######################################
# Post synthesis simulation (synth must have ran first)
[target.psim]
toolchain           = xsim

# Toolchain settings
toplevel            = tb_heartbeat
vcdlevels           = 20
runtime             = all
xelab_opts          = -maxdelay -transport_int_delays -L simprims_ver

# Fileset
files_vhdl          = SIM/tb_heartbeat.vhd
files_verilog       = OUT/synth/impl_netlist.v
#files_sysverilog   =
#files_xci          = 
files_other         = OUT/synth/impl_netlist.sdf
# ######################################

# ======================================
# PS/PL workflow
# ======================================

# ######################################
# Firmware compilation
[target.firmware]
toolchain           = make

# Toolchain settings
output_files        = build/app.elf DISASS
buildroot           = SW

# Fileset
files_makefile      = SW/Makefile
files_other         = SW/linker.ld
                      SW/src/boot.S
                      SW/src/main.c
                      SW/src/printf.c
                      SW/src/printf.h
                      SW/src/uart.c
                      SW/src/uart.h
                      SW/src/xil_io.h
                      SW/src/zynq.h
                      OUT/ip/zynqps/ps7_init.c
                      OUT/ip/zynqps/ps7_init.h
# ######################################


# ######################################
# Firmware simulation
[target.firmsim]
toolchain           = qemu

# Toolchain settings
arch                = arm
machine             = xilinx-zynq-a9
ram                 = 256M
extra_opts          = -serial /dev/null -serial mon:stdio

# Fileset
files_executable    = OUT/firmware/app.elf
# ######################################

# ######################################
# Device tree compilation
[target.devtree]
toolchain           = make

# Toolchain settings
output_files        = system.dtb system.dts
buildroot           = SW/devicetree

# Fileset
files_makefile      = SW/devicetree/Makefile
files_other         = SW/devicetree/pcw.dtsi
                      SW/devicetree/pl.dtsi
                      SW/devicetree/skeleton.dtsi
                      SW/devicetree/system-top.dts
                      SW/devicetree/zynq-7000.dtsi
                      SW/devicetree/zynq-pl-remoteport.dtsi
                      SW/devicetree/include/dt-bindings/clock/xlnx-versal-clk.h
                      SW/devicetree/include/dt-bindings/power/xlnx-versal-power.h
                      SW/devicetree/include/dt-bindings/reset/xlnx-versal-resets.h
# ######################################

# ######################################
# Hardware-firmware cosimulation PS part
[target.cosim_ps]
toolchain           = qemu

# Toolchain settings
arch                = xilinxarm
machine             = arm-generic-fdt-7series
ram                 = 256M
extra_opts          = -serial /dev/null -serial mon:stdio -dtb ../OUT/devtree/system.dtb \
                      -machine-path /tmp \
                      -icount 1 -sync-quantum 100000 \
                      -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4

# Fileset
files_executable    = OUT/firmware/app.elf
files_other         = OUT/devtree/system.dtb
# ######################################

# ######################################
# Hardware-firmware cosimulation PL part
# Note: currently not using xsim since compilation with xilinx 
# provided tools are horrible on linux
[target.cosim_pl]
toolchain           = questa

# Toolchain settings
toplevel            = tb_cosim
vcdlevels           = 20
runtime             = all

# Fileset
files_vhdl          = RTL/heartbeat.vhd
# files_verilog      =
files_sysverilog    = SIM/tb_cosim.sv
files_c             = SIM/c/remote-port-proto.c SIM/c/cosim.c
files_other         = SIM/c/remote-port-proto.h
# ######################################