Added qemu toolchain and created zynq ps targets

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/zynq7000/project.cfg

@@ -10,6 +10,10 @@ port                = 2020
 privkey             = /home/joppe/.ssh/id_rsa
 pubkey              = /home/joppe/.ssh/id_rsa.pub
 
+# ======================================
+# BASIC FPGA WORKFLOW
+# ======================================
+
 # ######################################
 # ISE IP block generation
 [target.ip]
@@ -92,10 +96,14 @@ files_verilog       = OUT/synth/impl_netlist.v
 files_other         = OUT/synth/impl_netlist.sdf
 # ######################################
 
+# ======================================
+# PS/PL workflow
+# ======================================
+
 # ######################################
 # Firmware compilation
 [target.firmware]
-toolchain           = gccmake
+toolchain           = make
 
 # Toolchain settings
 output_files        = build/app.elf DISASS
@@ -114,4 +122,42 @@ files_other         = SW/linker.ld
                       SW/src/zynq.h
                       OUT/ip/zynqps/ps7_init.c
                       OUT/ip/zynqps/ps7_init.h
+# ######################################
+
+
+# ######################################
+# Firmware simulation
+[target.firmsim]
+toolchain           = qemu
+
+# Toolchain settings
+arch                = arm
+machine             = xilinx-zynq-a9
+ram                 = 256M
+extra_opts          = -serial /dev/null -serial mon:stdio
+
+# Fileset
+files_executable    = OUT/firmware/app.elf
+# ######################################
+
+# ######################################
+# Device tree compilation
+[target.devtree]
+toolchain           = make
+
+# Toolchain settings
+output_files        = system.dtb system.dts
+buildroot           = SW/devicetree
+
+# Fileset
+files_makefile      = SW/devicetree/Makefile
+files_other         = SW/devicetree/pcw.dtsi
+                      SW/devicetree/pl.dtsi
+                      SW/devicetree/skeleton.dtsi
+                      SW/devicetree/system-top.dts
+                      SW/devicetree/zynq-7000.dtsi
+                      SW/devicetree/zynq-pl-remoteport.dtsi
+                      SW/devicetree/include/dt-bindings/clock/xlnx-versal-clk.h
+                      SW/devicetree/include/dt-bindings/power/xlnx-versal-power.h
+                      SW/devicetree/include/dt-bindings/reset/xlnx-versal-resets.h
 # ######################################