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Added qemu toolchain and created zynq ps targets

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-09 13:54:55 +02:00
parent 15d7e8b801
commit e18a0c1762
18 changed files with 1394 additions and 36 deletions
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examples/zynq7000/SW/devicetree/zynq-pl-remoteport.dtsi Normal file
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/*
* Zynq 7000 PL Interface over Remote-port.
*
* Copyright (c) 2016, Xilinx Inc
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&slcr {
/* In QEMU, the SLCR exports GPIOS (e.g the FPGA Resets). */
#gpio-cells = <1>;
gpio-controller;
};
/* Append stuff to the PS nodes. */
/ {
/* This version of the AMBA PL describes the PS/PL interface
* and not the devices that are available on the PL side.
*
* This is what QEMU will use to instantiate the RemotePort
* connections allowing for cosimulation.
*/
amba_pl {
cosim_rp_0: cosim@0 {
compatible = "remote-port";
sync = <1>;
chrdev-id = "pl-rp";
};
m_axi_gp0: rp_m_axi_gp0@40000000 {
compatible = "remote-port-memory-master";
remote-ports = < &cosim_rp_0 7 >;
reg = < 0x40000000 0x40000000 >;
};
m_axi_gp1: rp_m_axi_gp1@80000000 {
compatible = "remote-port-memory-master";
remote-ports = < &cosim_rp_0 8 >;
reg = < 0x80000000 0x40000000 >;
};
s_axi_gp0: rp_s_axi_gp0@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 0 >;
};
s_axi_gp1: rp_s_axi_gp1@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 1 >;
};
afi_0: rp_afi0@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 2 >;
};
afi_1: rp_afi1@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 3 >;
};
afi_2: rp_afi2@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 4 >;
};
afi_3: rp_afi3@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 5 >;
};
acp: rp_acp0@0 {
compatible = "remote-port-memory-slave";
remote-ports = < &cosim_rp_0 6 >;
};
wires_in: rp_wires_in@0 {
compatible = "remote-port-gpio";
remote-ports = < &cosim_rp_0 9 >;
num-gpios = < 16 >;
/* QEMU has a bug in the interrupts-extended parsing,
* so we need to use interrupt-parent for the moment.
*/
interrupt-parent = < &intc >;
interrupts = <
0x0 29 0x4
0x0 30 0x4
0x0 31 0x4
0x0 32 0x4
0x0 33 0x4
0x0 34 0x4
0x0 35 0x4
0x0 36 0x4
0x0 52 0x4
0x0 53 0x4
0x0 54 0x4
0x0 55 0x4
0x0 56 0x4
0x0 57 0x4
0x0 58 0x4
0x0 59 0x4
>;
};
wires_out: rp_wires_out@0 {
compatible = "remote-port-gpio";
remote-ports = < &cosim_rp_0 10 >;
num-gpios = <17>;
gpios = <
/* 17 FPGA_OUT_RESETS. */
&slcr 2 &slcr 3 &slcr 4 &slcr 5
&slcr 6 &slcr 7 &slcr 8 &slcr 9
&slcr 10 &slcr 11 &slcr 12 &slcr 13
&slcr 14 &slcr 15 &slcr 16 &slcr 17
&slcr 18
>;
};
rp_cosim_intr_pstopl: rp_cosim_intr_pstopl@0 {
#interrupt-cells = <3>;
interrupt-controller;
compatible = "remote-port-gpio";
remote-ports = <&cosim_rp_0 11>;
/* There are only 28 connections but due to the offset we need
* a higher number here.
*/
num-gpios = <96>;
cell-offset-irq-num = <1>;
};
/* This area can be used for implentation specific emulation*/
rp_cosim_reserved: rp_cosim_reserved@0{
compatible = "remote-port-memory-master";
remote-ports = <&cosim_rp_0 12>;
reg = <0xFE000000 0x100000>;
};
};
};
&can1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 0 4>, <0 0 0 &intc 0 51 4>;
};
&uart1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 1 4>, <0 0 0 &intc 0 50 4>;
};
&spi1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 2 4>, <0 0 0 &intc 0 49 4>;
};
&i2c1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 3 4>, <0 0 0 &intc 0 48 4>;
};
&sdhci1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 4 4>, <0 0 0 &intc 0 47 4>;
};
&gem1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 6 4>, <0 0 0 &intc 0 45 4>;
};
&usb1 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 7 4>, <0 0 0 &intc 0 44 4>;
};
&can0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 8 4>, <0 0 0 &intc 0 28 4>;
};
&spi0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 10 4>, <0 0 0 &intc 0 26 4>;
};
&i2c0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 11 4>, <0 0 0 &intc 0 25 4>;
};
&sdhci0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 12 4>, <0 0 0 &intc 0 24 4>;
};
&gem0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 14 4>, <0 0 0 &intc 0 22 4>;
};
&usb0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 15 4>, <0 0 0 &intc 0 21 4>;
};
&gpio0 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 16 4>, <0 0 0 &intc 0 20 4>;
};
&qspi {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 18 4>, <0 0 0 &intc 0 19 4>;
};
&smcc {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 19 4>, <0 0 0 &intc 0 18 4>;
};
&dmac_s {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 28 4>, <0 0 0 &intc 0 13 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 20 4>, <0 0 0 &intc 0 14 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 21 4>, <0 0 0 &intc 0 15 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 22 4>, <0 0 0 &intc 0 16 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 23 4>, <0 0 0 &intc 0 17 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 24 4>, <0 0 0 &intc 0 40 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 25 4>, <0 0 0 &intc 0 41 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 26 4>, <0 0 0 &intc 0 42 4>,
<0 0 0 &rp_cosim_intr_pstopl 0 27 4>, <0 0 0 &intc 0 43 4>;
};