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Added qemu toolchain and created zynq ps targets

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-09 13:54:55 +02:00
parent 15d7e8b801
commit e18a0c1762
18 changed files with 1394 additions and 36 deletions
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123
examples/zynq7000/SW/devicetree/include/dt-bindings/clock/xlnx-versal-clk.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Xilinx Inc.
*
*/
#ifndef _DT_BINDINGS_CLK_VERSAL_H
#define _DT_BINDINGS_CLK_VERSAL_H
#define PMC_PLL 1
#define APU_PLL 2
#define RPU_PLL 3
#define CPM_PLL 4
#define NOC_PLL 5
#define PLL_MAX 6
#define PMC_PRESRC 7
#define PMC_POSTCLK 8
#define PMC_PLL_OUT 9
#define PPLL 10
#define NOC_PRESRC 11
#define NOC_POSTCLK 12
#define NOC_PLL_OUT 13
#define NPLL 14
#define APU_PRESRC 15
#define APU_POSTCLK 16
#define APU_PLL_OUT 17
#define APLL 18
#define RPU_PRESRC 19
#define RPU_POSTCLK 20
#define RPU_PLL_OUT 21
#define RPLL 22
#define CPM_PRESRC 23
#define CPM_POSTCLK 24
#define CPM_PLL_OUT 25
#define CPLL 26
#define PPLL_TO_XPD 27
#define NPLL_TO_XPD 28
#define APLL_TO_XPD 29
#define RPLL_TO_XPD 30
#define EFUSE_REF 31
#define SYSMON_REF 32
#define IRO_SUSPEND_REF 33
#define USB_SUSPEND 34
#define SWITCH_TIMEOUT 35
#define RCLK_PMC 36
#define RCLK_LPD 37
#define WDT 38
#define TTC0 39
#define TTC1 40
#define TTC2 41
#define TTC3 42
#define GEM_TSU 43
#define GEM_TSU_LB 44
#define MUXED_IRO_DIV2 45
#define MUXED_IRO_DIV4 46
#define PSM_REF 47
#define GEM0_RX 48
#define GEM0_TX 49
#define GEM1_RX 50
#define GEM1_TX 51
#define CPM_CORE_REF 52
#define CPM_LSBUS_REF 53
#define CPM_DBG_REF 54
#define CPM_AUX0_REF 55
#define CPM_AUX1_REF 56
#define QSPI_REF 57
#define OSPI_REF 58
#define SDIO0_REF 59
#define SDIO1_REF 60
#define PMC_LSBUS_REF 61
#define I2C_REF 62
#define TEST_PATTERN_REF 63
#define DFT_OSC_REF 64
#define PMC_PL0_REF 65
#define PMC_PL1_REF 66
#define PMC_PL2_REF 67
#define PMC_PL3_REF 68
#define CFU_REF 69
#define SPARE_REF 70
#define NPI_REF 71
#define HSM0_REF 72
#define HSM1_REF 73
#define SD_DLL_REF 74
#define FPD_TOP_SWITCH 75
#define FPD_LSBUS 76
#define ACPU 77
#define DBG_TRACE 78
#define DBG_FPD 79
#define LPD_TOP_SWITCH 80
#define ADMA 81
#define LPD_LSBUS 82
#define CPU_R5 83
#define CPU_R5_CORE 84
#define CPU_R5_OCM 85
#define CPU_R5_OCM2 86
#define IOU_SWITCH 87
#define GEM0_REF 88
#define GEM1_REF 89
#define GEM_TSU_REF 90
#define USB0_BUS_REF 91
#define UART0_REF 92
#define UART1_REF 93
#define SPI0_REF 94
#define SPI1_REF 95
#define CAN0_REF 96
#define CAN1_REF 97
#define I2C0_REF 98
#define I2C1_REF 99
#define DBG_LPD 100
#define TIMESTAMP_REF 101
#define DBG_TSTMP 102
#define CPM_TOPSW_REF 103
#define USB3_DUAL_REF 104
#define OUTCLK_MAX 105
#define REF_CLK 106
#define PL_ALT_REF_CLK 107
#define MUXED_IRO 108
#define PL_EXT 109
#define PL_LB 110
#define MIO_50_OR_51 111
#define MIO_24_OR_25 112
#endif

42
examples/zynq7000/SW/devicetree/include/dt-bindings/power/xlnx-versal-power.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_VERSAL_POWER_H
#define _DT_BINDINGS_VERSAL_POWER_H
#define PM_DEV_USB_0 (0x18224018U)
#define PM_DEV_GEM_0 (0x18224019U)
#define PM_DEV_GEM_1 (0x1822401aU)
#define PM_DEV_SPI_0 (0x1822401bU)
#define PM_DEV_SPI_1 (0x1822401cU)
#define PM_DEV_I2C_0 (0x1822401dU)
#define PM_DEV_I2C_1 (0x1822401eU)
#define PM_DEV_CAN_FD_0 (0x1822401fU)
#define PM_DEV_CAN_FD_1 (0x18224020U)
#define PM_DEV_UART_0 (0x18224021U)
#define PM_DEV_UART_1 (0x18224022U)
#define PM_DEV_GPIO (0x18224023U)
#define PM_DEV_TTC_0 (0x18224024U)
#define PM_DEV_TTC_1 (0x18224025U)
#define PM_DEV_TTC_2 (0x18224026U)
#define PM_DEV_TTC_3 (0x18224027U)
#define PM_DEV_SWDT_FPD (0x18224029U)
#define PM_DEV_OSPI (0x1822402aU)
#define PM_DEV_QSPI (0x1822402bU)
#define PM_DEV_GPIO_PMC (0x1822402cU)
#define PM_DEV_SDIO_0 (0x1822402eU)
#define PM_DEV_SDIO_1 (0x1822402fU)
#define PM_DEV_RTC (0x18224034U)
#define PM_DEV_ADMA_0 (0x18224035U)
#define PM_DEV_ADMA_1 (0x18224036U)
#define PM_DEV_ADMA_2 (0x18224037U)
#define PM_DEV_ADMA_3 (0x18224038U)
#define PM_DEV_ADMA_4 (0x18224039U)
#define PM_DEV_ADMA_5 (0x1822403aU)
#define PM_DEV_ADMA_6 (0x1822403bU)
#define PM_DEV_ADMA_7 (0x1822403cU)
#define PM_DEV_AI (0x18224072U)
#endif

130
examples/zynq7000/SW/devicetree/include/dt-bindings/reset/xlnx-versal-resets.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
#define _DT_BINDINGS_ZYNQMP_RESETS_H
#define ZYNQMP_RESET_PCIE_CFG 0
#define ZYNQMP_RESET_PCIE_BRIDGE 1
#define ZYNQMP_RESET_PCIE_CTRL 2
#define ZYNQMP_RESET_DP 3
#define ZYNQMP_RESET_SWDT_CRF 4
#define ZYNQMP_RESET_AFI_FM5 5
#define ZYNQMP_RESET_AFI_FM4 6
#define ZYNQMP_RESET_AFI_FM3 7
#define ZYNQMP_RESET_AFI_FM2 8
#define ZYNQMP_RESET_AFI_FM1 9
#define ZYNQMP_RESET_AFI_FM0 10
#define ZYNQMP_RESET_GDMA 11
#define ZYNQMP_RESET_GPU_PP1 12
#define ZYNQMP_RESET_GPU_PP0 13
#define ZYNQMP_RESET_GPU 14
#define ZYNQMP_RESET_GT 15
#define ZYNQMP_RESET_SATA 16
#define ZYNQMP_RESET_ACPU3_PWRON 17
#define ZYNQMP_RESET_ACPU2_PWRON 18
#define ZYNQMP_RESET_ACPU1_PWRON 19
#define ZYNQMP_RESET_ACPU0_PWRON 20
#define ZYNQMP_RESET_APU_L2 21
#define ZYNQMP_RESET_ACPU3 22
#define ZYNQMP_RESET_ACPU2 23
#define ZYNQMP_RESET_ACPU1 24
#define ZYNQMP_RESET_ACPU0 25
#define ZYNQMP_RESET_DDR 26
#define ZYNQMP_RESET_APM_FPD 27
#define ZYNQMP_RESET_SOFT 28
#define ZYNQMP_RESET_GEM0 29
#define ZYNQMP_RESET_GEM1 30
#define ZYNQMP_RESET_GEM2 31
#define ZYNQMP_RESET_GEM3 32
#define ZYNQMP_RESET_QSPI 33
#define ZYNQMP_RESET_UART0 34
#define ZYNQMP_RESET_UART1 35
#define ZYNQMP_RESET_SPI0 36
#define ZYNQMP_RESET_SPI1 37
#define ZYNQMP_RESET_SDIO0 38
#define ZYNQMP_RESET_SDIO1 39
#define ZYNQMP_RESET_CAN0 40
#define ZYNQMP_RESET_CAN1 41
#define ZYNQMP_RESET_I2C0 42
#define ZYNQMP_RESET_I2C1 43
#define ZYNQMP_RESET_TTC0 44
#define ZYNQMP_RESET_TTC1 45
#define ZYNQMP_RESET_TTC2 46
#define ZYNQMP_RESET_TTC3 47
#define ZYNQMP_RESET_SWDT_CRL 48
#define ZYNQMP_RESET_NAND 49
#define ZYNQMP_RESET_ADMA 50
#define ZYNQMP_RESET_GPIO 51
#define ZYNQMP_RESET_IOU_CC 52
#define ZYNQMP_RESET_TIMESTAMP 53
#define ZYNQMP_RESET_RPU_R50 54
#define ZYNQMP_RESET_RPU_R51 55
#define ZYNQMP_RESET_RPU_AMBA 56
#define ZYNQMP_RESET_OCM 57
#define ZYNQMP_RESET_RPU_PGE 58
#define ZYNQMP_RESET_USB0_CORERESET 59
#define ZYNQMP_RESET_USB1_CORERESET 60
#define ZYNQMP_RESET_USB0_HIBERRESET 61
#define ZYNQMP_RESET_USB1_HIBERRESET 62
#define ZYNQMP_RESET_USB0_APB 63
#define ZYNQMP_RESET_USB1_APB 64
#define ZYNQMP_RESET_IPI 65
#define ZYNQMP_RESET_APM_LPD 66
#define ZYNQMP_RESET_RTC 67
#define ZYNQMP_RESET_SYSMON 68
#define ZYNQMP_RESET_AFI_FM6 69
#define ZYNQMP_RESET_LPD_SWDT 70
#define ZYNQMP_RESET_FPD 71
#define ZYNQMP_RESET_RPU_DBG1 72
#define ZYNQMP_RESET_RPU_DBG0 73
#define ZYNQMP_RESET_DBG_LPD 74
#define ZYNQMP_RESET_DBG_FPD 75
#define ZYNQMP_RESET_APLL 76
#define ZYNQMP_RESET_DPLL 77
#define ZYNQMP_RESET_VPLL 78
#define ZYNQMP_RESET_IOPLL 79
#define ZYNQMP_RESET_RPLL 80
#define ZYNQMP_RESET_GPO3_PL_0 81
#define ZYNQMP_RESET_GPO3_PL_1 82
#define ZYNQMP_RESET_GPO3_PL_2 83
#define ZYNQMP_RESET_GPO3_PL_3 84
#define ZYNQMP_RESET_GPO3_PL_4 85
#define ZYNQMP_RESET_GPO3_PL_5 86
#define ZYNQMP_RESET_GPO3_PL_6 87
#define ZYNQMP_RESET_GPO3_PL_7 88
#define ZYNQMP_RESET_GPO3_PL_8 89
#define ZYNQMP_RESET_GPO3_PL_9 90
#define ZYNQMP_RESET_GPO3_PL_10 91
#define ZYNQMP_RESET_GPO3_PL_11 92
#define ZYNQMP_RESET_GPO3_PL_12 93
#define ZYNQMP_RESET_GPO3_PL_13 94
#define ZYNQMP_RESET_GPO3_PL_14 95
#define ZYNQMP_RESET_GPO3_PL_15 96
#define ZYNQMP_RESET_GPO3_PL_16 97
#define ZYNQMP_RESET_GPO3_PL_17 98
#define ZYNQMP_RESET_GPO3_PL_18 99
#define ZYNQMP_RESET_GPO3_PL_19 100
#define ZYNQMP_RESET_GPO3_PL_20 101
#define ZYNQMP_RESET_GPO3_PL_21 102
#define ZYNQMP_RESET_GPO3_PL_22 103
#define ZYNQMP_RESET_GPO3_PL_23 104
#define ZYNQMP_RESET_GPO3_PL_24 105
#define ZYNQMP_RESET_GPO3_PL_25 106
#define ZYNQMP_RESET_GPO3_PL_26 107
#define ZYNQMP_RESET_GPO3_PL_27 108
#define ZYNQMP_RESET_GPO3_PL_28 109
#define ZYNQMP_RESET_GPO3_PL_29 110
#define ZYNQMP_RESET_GPO3_PL_30 111
#define ZYNQMP_RESET_GPO3_PL_31 112
#define ZYNQMP_RESET_RPU_LS 113
#define ZYNQMP_RESET_PS_ONLY 114
#define ZYNQMP_RESET_PL 115
#define ZYNQMP_RESET_PS_PL0 116
#define ZYNQMP_RESET_PS_PL1 117
#define ZYNQMP_RESET_PS_PL2 118
#define ZYNQMP_RESET_PS_PL3 119
#endif