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Added qemu toolchain and created zynq ps targets

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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Joppe Blondel
2022-09-09 13:54:55 +02:00
parent 15d7e8b801
commit e18a0c1762
18 changed files with 1394 additions and 36 deletions
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examples/zynq7000/README.md Normal file
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# ZYNQ 7 series project
### Basic FPGA workflow
+ target `ip`: Generate IP blocks defined in the tcl files in the IP directory
+ target `synth`: Synthesize design
+ target `sim`: Behavioural simulation of part of the design
+ target `psim`: Post synthesis simulation of mentioned part of the design
### ZYNQ SoC workflos
+ target `firmware`: Compile the firmware running on the ARM core(s) with the `make` toolchain
+ target `firmsim`: Simulate the firmware with QEMU without PS/PL cosimulation with the `qemu` toolchain
+ target `devtree`: Compile the device tree for a PS/PL cosimulation with QEMU