Added qemu toolchain and created zynq ps targets
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
12
examples/zynq7000/README.md
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12
examples/zynq7000/README.md
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@ -0,0 +1,12 @@
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# ZYNQ 7 series project
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### Basic FPGA workflow
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+ target `ip`: Generate IP blocks defined in the tcl files in the IP directory
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+ target `synth`: Synthesize design
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+ target `sim`: Behavioural simulation of part of the design
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+ target `psim`: Post synthesis simulation of mentioned part of the design
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### ZYNQ SoC workflos
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+ target `firmware`: Compile the firmware running on the ARM core(s) with the `make` toolchain
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+ target `firmsim`: Simulate the firmware with QEMU without PS/PL cosimulation with the `qemu` toolchain
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+ target `devtree`: Compile the device tree for a PS/PL cosimulation with QEMU
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13
examples/zynq7000/SW/devicetree/Makefile
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13
examples/zynq7000/SW/devicetree/Makefile
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.SILENT:
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TARGET := system.dtb
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BUILDROOT ?= $(shell pwd)
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BUILDDIR := build
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.PHONY: $(TARGET) all clean
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all: $(TARGET)
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$(TARGET):
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gcc -I $(BUILDROOT) -I $(BUILDROOT)/include -E -nostdinc -undef -D__DTS__ -x assembler-with-cpp -o system.dts $(BUILDROOT)/system-top.dts
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dtc -I dts -O dtb -o system.dtb system.dts
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@ -0,0 +1,123 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Xilinx Inc.
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*
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*/
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#ifndef _DT_BINDINGS_CLK_VERSAL_H
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#define _DT_BINDINGS_CLK_VERSAL_H
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#define PMC_PLL 1
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#define APU_PLL 2
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#define RPU_PLL 3
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#define CPM_PLL 4
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#define NOC_PLL 5
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#define PLL_MAX 6
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#define PMC_PRESRC 7
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#define PMC_POSTCLK 8
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#define PMC_PLL_OUT 9
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#define PPLL 10
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#define NOC_PRESRC 11
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#define NOC_POSTCLK 12
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#define NOC_PLL_OUT 13
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#define NPLL 14
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#define APU_PRESRC 15
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#define APU_POSTCLK 16
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#define APU_PLL_OUT 17
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#define APLL 18
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#define RPU_PRESRC 19
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#define RPU_POSTCLK 20
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#define RPU_PLL_OUT 21
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#define RPLL 22
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#define CPM_PRESRC 23
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#define CPM_POSTCLK 24
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#define CPM_PLL_OUT 25
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#define CPLL 26
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#define PPLL_TO_XPD 27
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#define NPLL_TO_XPD 28
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#define APLL_TO_XPD 29
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#define RPLL_TO_XPD 30
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#define EFUSE_REF 31
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#define SYSMON_REF 32
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#define IRO_SUSPEND_REF 33
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#define USB_SUSPEND 34
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#define SWITCH_TIMEOUT 35
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#define RCLK_PMC 36
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#define RCLK_LPD 37
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#define WDT 38
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#define TTC0 39
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#define TTC1 40
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#define TTC2 41
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#define TTC3 42
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#define GEM_TSU 43
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#define GEM_TSU_LB 44
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#define MUXED_IRO_DIV2 45
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#define MUXED_IRO_DIV4 46
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#define PSM_REF 47
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#define GEM0_RX 48
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#define GEM0_TX 49
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#define GEM1_RX 50
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#define GEM1_TX 51
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#define CPM_CORE_REF 52
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#define CPM_LSBUS_REF 53
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#define CPM_DBG_REF 54
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#define CPM_AUX0_REF 55
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#define CPM_AUX1_REF 56
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#define QSPI_REF 57
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#define OSPI_REF 58
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#define SDIO0_REF 59
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#define SDIO1_REF 60
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#define PMC_LSBUS_REF 61
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#define I2C_REF 62
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#define TEST_PATTERN_REF 63
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#define DFT_OSC_REF 64
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#define PMC_PL0_REF 65
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#define PMC_PL1_REF 66
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#define PMC_PL2_REF 67
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#define PMC_PL3_REF 68
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#define CFU_REF 69
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#define SPARE_REF 70
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#define NPI_REF 71
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#define HSM0_REF 72
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#define HSM1_REF 73
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#define SD_DLL_REF 74
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#define FPD_TOP_SWITCH 75
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#define FPD_LSBUS 76
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#define ACPU 77
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#define DBG_TRACE 78
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#define DBG_FPD 79
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#define LPD_TOP_SWITCH 80
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#define ADMA 81
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#define LPD_LSBUS 82
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#define CPU_R5 83
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#define CPU_R5_CORE 84
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#define CPU_R5_OCM 85
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#define CPU_R5_OCM2 86
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#define IOU_SWITCH 87
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#define GEM0_REF 88
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#define GEM1_REF 89
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#define GEM_TSU_REF 90
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#define USB0_BUS_REF 91
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#define UART0_REF 92
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#define UART1_REF 93
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#define SPI0_REF 94
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#define SPI1_REF 95
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#define CAN0_REF 96
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#define CAN1_REF 97
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#define I2C0_REF 98
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#define I2C1_REF 99
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#define DBG_LPD 100
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#define TIMESTAMP_REF 101
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#define DBG_TSTMP 102
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#define CPM_TOPSW_REF 103
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#define USB3_DUAL_REF 104
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#define OUTCLK_MAX 105
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#define REF_CLK 106
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#define PL_ALT_REF_CLK 107
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#define MUXED_IRO 108
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#define PL_EXT 109
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#define PL_LB 110
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#define MIO_50_OR_51 111
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#define MIO_24_OR_25 112
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#endif
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@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_VERSAL_POWER_H
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#define _DT_BINDINGS_VERSAL_POWER_H
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#define PM_DEV_USB_0 (0x18224018U)
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#define PM_DEV_GEM_0 (0x18224019U)
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#define PM_DEV_GEM_1 (0x1822401aU)
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#define PM_DEV_SPI_0 (0x1822401bU)
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#define PM_DEV_SPI_1 (0x1822401cU)
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#define PM_DEV_I2C_0 (0x1822401dU)
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#define PM_DEV_I2C_1 (0x1822401eU)
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#define PM_DEV_CAN_FD_0 (0x1822401fU)
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#define PM_DEV_CAN_FD_1 (0x18224020U)
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#define PM_DEV_UART_0 (0x18224021U)
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#define PM_DEV_UART_1 (0x18224022U)
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#define PM_DEV_GPIO (0x18224023U)
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#define PM_DEV_TTC_0 (0x18224024U)
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#define PM_DEV_TTC_1 (0x18224025U)
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#define PM_DEV_TTC_2 (0x18224026U)
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#define PM_DEV_TTC_3 (0x18224027U)
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#define PM_DEV_SWDT_FPD (0x18224029U)
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#define PM_DEV_OSPI (0x1822402aU)
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#define PM_DEV_QSPI (0x1822402bU)
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#define PM_DEV_GPIO_PMC (0x1822402cU)
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#define PM_DEV_SDIO_0 (0x1822402eU)
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#define PM_DEV_SDIO_1 (0x1822402fU)
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#define PM_DEV_RTC (0x18224034U)
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#define PM_DEV_ADMA_0 (0x18224035U)
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#define PM_DEV_ADMA_1 (0x18224036U)
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#define PM_DEV_ADMA_2 (0x18224037U)
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#define PM_DEV_ADMA_3 (0x18224038U)
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#define PM_DEV_ADMA_4 (0x18224039U)
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#define PM_DEV_ADMA_5 (0x1822403aU)
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#define PM_DEV_ADMA_6 (0x1822403bU)
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#define PM_DEV_ADMA_7 (0x1822403cU)
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#define PM_DEV_AI (0x18224072U)
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#endif
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@ -0,0 +1,130 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
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#define _DT_BINDINGS_ZYNQMP_RESETS_H
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#define ZYNQMP_RESET_PCIE_CFG 0
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#define ZYNQMP_RESET_PCIE_BRIDGE 1
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#define ZYNQMP_RESET_PCIE_CTRL 2
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#define ZYNQMP_RESET_DP 3
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#define ZYNQMP_RESET_SWDT_CRF 4
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#define ZYNQMP_RESET_AFI_FM5 5
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#define ZYNQMP_RESET_AFI_FM4 6
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#define ZYNQMP_RESET_AFI_FM3 7
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#define ZYNQMP_RESET_AFI_FM2 8
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#define ZYNQMP_RESET_AFI_FM1 9
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#define ZYNQMP_RESET_AFI_FM0 10
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#define ZYNQMP_RESET_GDMA 11
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#define ZYNQMP_RESET_GPU_PP1 12
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#define ZYNQMP_RESET_GPU_PP0 13
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#define ZYNQMP_RESET_GPU 14
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#define ZYNQMP_RESET_GT 15
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#define ZYNQMP_RESET_SATA 16
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#define ZYNQMP_RESET_ACPU3_PWRON 17
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#define ZYNQMP_RESET_ACPU2_PWRON 18
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#define ZYNQMP_RESET_ACPU1_PWRON 19
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#define ZYNQMP_RESET_ACPU0_PWRON 20
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#define ZYNQMP_RESET_APU_L2 21
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#define ZYNQMP_RESET_ACPU3 22
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#define ZYNQMP_RESET_ACPU2 23
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#define ZYNQMP_RESET_ACPU1 24
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#define ZYNQMP_RESET_ACPU0 25
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#define ZYNQMP_RESET_DDR 26
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#define ZYNQMP_RESET_APM_FPD 27
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#define ZYNQMP_RESET_SOFT 28
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#define ZYNQMP_RESET_GEM0 29
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#define ZYNQMP_RESET_GEM1 30
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#define ZYNQMP_RESET_GEM2 31
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#define ZYNQMP_RESET_GEM3 32
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#define ZYNQMP_RESET_QSPI 33
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#define ZYNQMP_RESET_UART0 34
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#define ZYNQMP_RESET_UART1 35
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#define ZYNQMP_RESET_SPI0 36
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#define ZYNQMP_RESET_SPI1 37
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#define ZYNQMP_RESET_SDIO0 38
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#define ZYNQMP_RESET_SDIO1 39
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#define ZYNQMP_RESET_CAN0 40
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#define ZYNQMP_RESET_CAN1 41
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#define ZYNQMP_RESET_I2C0 42
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#define ZYNQMP_RESET_I2C1 43
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#define ZYNQMP_RESET_TTC0 44
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#define ZYNQMP_RESET_TTC1 45
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#define ZYNQMP_RESET_TTC2 46
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#define ZYNQMP_RESET_TTC3 47
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#define ZYNQMP_RESET_SWDT_CRL 48
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#define ZYNQMP_RESET_NAND 49
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#define ZYNQMP_RESET_ADMA 50
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#define ZYNQMP_RESET_GPIO 51
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#define ZYNQMP_RESET_IOU_CC 52
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#define ZYNQMP_RESET_TIMESTAMP 53
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#define ZYNQMP_RESET_RPU_R50 54
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#define ZYNQMP_RESET_RPU_R51 55
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#define ZYNQMP_RESET_RPU_AMBA 56
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#define ZYNQMP_RESET_OCM 57
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#define ZYNQMP_RESET_RPU_PGE 58
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#define ZYNQMP_RESET_USB0_CORERESET 59
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#define ZYNQMP_RESET_USB1_CORERESET 60
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#define ZYNQMP_RESET_USB0_HIBERRESET 61
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#define ZYNQMP_RESET_USB1_HIBERRESET 62
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#define ZYNQMP_RESET_USB0_APB 63
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#define ZYNQMP_RESET_USB1_APB 64
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#define ZYNQMP_RESET_IPI 65
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#define ZYNQMP_RESET_APM_LPD 66
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#define ZYNQMP_RESET_RTC 67
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#define ZYNQMP_RESET_SYSMON 68
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#define ZYNQMP_RESET_AFI_FM6 69
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#define ZYNQMP_RESET_LPD_SWDT 70
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#define ZYNQMP_RESET_FPD 71
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#define ZYNQMP_RESET_RPU_DBG1 72
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#define ZYNQMP_RESET_RPU_DBG0 73
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#define ZYNQMP_RESET_DBG_LPD 74
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#define ZYNQMP_RESET_DBG_FPD 75
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#define ZYNQMP_RESET_APLL 76
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#define ZYNQMP_RESET_DPLL 77
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#define ZYNQMP_RESET_VPLL 78
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#define ZYNQMP_RESET_IOPLL 79
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#define ZYNQMP_RESET_RPLL 80
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#define ZYNQMP_RESET_GPO3_PL_0 81
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#define ZYNQMP_RESET_GPO3_PL_1 82
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#define ZYNQMP_RESET_GPO3_PL_2 83
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#define ZYNQMP_RESET_GPO3_PL_3 84
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#define ZYNQMP_RESET_GPO3_PL_4 85
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#define ZYNQMP_RESET_GPO3_PL_5 86
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#define ZYNQMP_RESET_GPO3_PL_6 87
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#define ZYNQMP_RESET_GPO3_PL_7 88
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#define ZYNQMP_RESET_GPO3_PL_8 89
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#define ZYNQMP_RESET_GPO3_PL_9 90
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#define ZYNQMP_RESET_GPO3_PL_10 91
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#define ZYNQMP_RESET_GPO3_PL_11 92
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#define ZYNQMP_RESET_GPO3_PL_12 93
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#define ZYNQMP_RESET_GPO3_PL_13 94
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#define ZYNQMP_RESET_GPO3_PL_14 95
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#define ZYNQMP_RESET_GPO3_PL_15 96
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#define ZYNQMP_RESET_GPO3_PL_16 97
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#define ZYNQMP_RESET_GPO3_PL_17 98
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#define ZYNQMP_RESET_GPO3_PL_18 99
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#define ZYNQMP_RESET_GPO3_PL_19 100
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#define ZYNQMP_RESET_GPO3_PL_20 101
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#define ZYNQMP_RESET_GPO3_PL_21 102
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#define ZYNQMP_RESET_GPO3_PL_22 103
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#define ZYNQMP_RESET_GPO3_PL_23 104
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#define ZYNQMP_RESET_GPO3_PL_24 105
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#define ZYNQMP_RESET_GPO3_PL_25 106
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#define ZYNQMP_RESET_GPO3_PL_26 107
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#define ZYNQMP_RESET_GPO3_PL_27 108
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#define ZYNQMP_RESET_GPO3_PL_28 109
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#define ZYNQMP_RESET_GPO3_PL_29 110
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#define ZYNQMP_RESET_GPO3_PL_30 111
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#define ZYNQMP_RESET_GPO3_PL_31 112
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#define ZYNQMP_RESET_RPU_LS 113
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#define ZYNQMP_RESET_PS_ONLY 114
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#define ZYNQMP_RESET_PL 115
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#define ZYNQMP_RESET_PS_PL0 116
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#define ZYNQMP_RESET_PS_PL1 117
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#define ZYNQMP_RESET_PS_PL2 118
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#define ZYNQMP_RESET_PS_PL3 119
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#endif
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28
examples/zynq7000/SW/devicetree/pcw.dtsi
Normal file
28
examples/zynq7000/SW/devicetree/pcw.dtsi
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* CAUTION: This file is automatically generated by Xilinx.
|
||||
* Version: XSCT 2020.2
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* Today is: Wed Oct 13 14:26:41 2021
|
||||
*/
|
||||
|
||||
|
||||
/ {
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||||
cpus {
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||||
cpu@0 {
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||||
operating-points = <666666 1000000 333333 1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
&intc {
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||||
num_cpus = <2>;
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||||
num_interrupts = <96>;
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||||
};
|
||||
&uart1 {
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||||
cts-override ;
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||||
device_type = "serial";
|
||||
port-number = <0>;
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||||
status = "okay";
|
||||
};
|
||||
&clkc {
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||||
fclk-enable = <0x1>;
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||||
ps-clk-frequency = <33333333>;
|
||||
};
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||||
35
examples/zynq7000/SW/devicetree/pl.dtsi
Normal file
35
examples/zynq7000/SW/devicetree/pl.dtsi
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* CAUTION: This file is automatically generated by Xilinx.
|
||||
* Version: XSCT 2020.2
|
||||
* Today is: Wed Oct 13 14:26:41 2021
|
||||
*/
|
||||
|
||||
|
||||
/ {
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||||
amba_pl: amba_pl {
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||||
#address-cells = <1>;
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||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
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||||
ranges ;
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||||
axi_gpio_0: gpio@41200000 {
|
||||
#gpio-cells = <3>;
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||||
clock-names = "s_axi_aclk";
|
||||
clocks = <&clkc 15>;
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||||
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
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||||
gpio-controller ;
|
||||
reg = <0x41200000 0x10000>;
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||||
xlnx,all-inputs = <0x0>;
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||||
xlnx,all-inputs-2 = <0x0>;
|
||||
xlnx,all-outputs = <0x0>;
|
||||
xlnx,all-outputs-2 = <0x0>;
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||||
xlnx,dout-default = <0x00000000>;
|
||||
xlnx,dout-default-2 = <0x00000000>;
|
||||
xlnx,gpio-width = <0x20>;
|
||||
xlnx,gpio2-width = <0x20>;
|
||||
xlnx,interrupt-present = <0x0>;
|
||||
xlnx,is-dual = <0x0>;
|
||||
xlnx,tri-default = <0xFFFFFFFF>;
|
||||
xlnx,tri-default-2 = <0xFFFFFFFF>;
|
||||
};
|
||||
};
|
||||
};
|
||||
13
examples/zynq7000/SW/devicetree/skeleton.dtsi
Normal file
13
examples/zynq7000/SW/devicetree/skeleton.dtsi
Normal file
@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Skeleton device tree; the bare minimum needed to boot; just include and
|
||||
* add a compatible value. The bootloader will typically populate the memory
|
||||
* node.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
chosen { };
|
||||
aliases { };
|
||||
memory { device_type = "memory"; reg = <0 0>; };
|
||||
};
|
||||
25
examples/zynq7000/SW/devicetree/system-top.dts
Normal file
25
examples/zynq7000/SW/devicetree/system-top.dts
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* CAUTION: This file is automatically generated by Xilinx.
|
||||
* Version: XSCT 2020.2
|
||||
* Today is: Wed Oct 13 14:26:41 2021
|
||||
*/
|
||||
|
||||
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
#include "zynq-pl-remoteport.dtsi"
|
||||
//#include "pl.dtsi"
|
||||
#include "pcw.dtsi"
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>;
|
||||
};
|
||||
};
|
||||
566
examples/zynq7000/SW/devicetree/zynq-7000.dtsi
Normal file
566
examples/zynq7000/SW/devicetree/zynq-7000.dtsi
Normal file
@ -0,0 +1,566 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2011 - 2015 Xilinx
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,zynq-7000";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&clkc 3>;
|
||||
clock-latency = <1000>;
|
||||
cpu0-supply = <®ulator_vccpint>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
666667 1000000
|
||||
333334 1000000
|
||||
>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&clkc 3>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga_full: fpga-full {
|
||||
compatible = "fpga-region";
|
||||
fpga-mgr = <&devcfg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pmu@f8891000 {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 5 4>, <0 6 4>;
|
||||
interrupt-parent = <&intc>;
|
||||
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
|
||||
};
|
||||
|
||||
regulator_vccpint: fixedregulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCCPINT";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
replicator {
|
||||
compatible = "arm,coresight-static-replicator";
|
||||
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&etb_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
in-ports {
|
||||
/* replicator input port */
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
remote-endpoint = <&funnel_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
amba: amba {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
adc: adc@f8007100 {
|
||||
compatible = "xlnx,zynq-xadc-1.00.a";
|
||||
reg = <0xf8007100 0x20>;
|
||||
interrupts = <0 7 4>;
|
||||
interrupt-parent = <&intc>;
|
||||
clocks = <&clkc 12>;
|
||||
};
|
||||
|
||||
can0: can@e0008000 {
|
||||
compatible = "xlnx,zynq-can-1.0";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 19>, <&clkc 36>;
|
||||
clock-names = "can_clk", "pclk";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
interrupts = <0 28 4>;
|
||||
interrupt-parent = <&intc>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
};
|
||||
|
||||
can1: can@e0009000 {
|
||||
compatible = "xlnx,zynq-can-1.0";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 20>, <&clkc 37>;
|
||||
clock-names = "can_clk", "pclk";
|
||||
reg = <0xe0009000 0x1000>;
|
||||
interrupts = <0 51 4>;
|
||||
interrupt-parent = <&intc>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e000a000 {
|
||||
compatible = "xlnx,zynq-gpio-1.0";
|
||||
#gpio-cells = <2>;
|
||||
clocks = <&clkc 42>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 20 4>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e0004000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 38>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 25 4>;
|
||||
reg = <0xe0004000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@e0005000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 39>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0xe0005000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@f8f01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xF8F01000 0x1000>,
|
||||
<0xF8F00100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@f8f02000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xF8F02000 0x1000>;
|
||||
interrupts = <0 2 4>;
|
||||
arm,data-latency = <3 2 2>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
mc: memory-controller@f8006000 {
|
||||
compatible = "xlnx,zynq-ddrc-a05";
|
||||
reg = <0xf8006000 0x1000>;
|
||||
};
|
||||
|
||||
ocmc: ocmc@f800c000 {
|
||||
compatible = "xlnx,zynq-ocmc-1.0";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 3 4>;
|
||||
reg = <0xf800c000 0x1000>;
|
||||
};
|
||||
|
||||
uart0: serial@e0000000 {
|
||||
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 23>, <&clkc 40>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
reg = <0xE0000000 0x1000>;
|
||||
interrupts = <0 27 4>;
|
||||
};
|
||||
|
||||
uart1: serial@e0001000 {
|
||||
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 24>, <&clkc 41>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
reg = <0xE0001000 0x1000>;
|
||||
interrupts = <0 50 4>;
|
||||
};
|
||||
|
||||
spi0: spi@e0006000 {
|
||||
compatible = "xlnx,zynq-spi-r1p6";
|
||||
reg = <0xe0006000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&clkc 25>, <&clkc 34>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@e0007000 {
|
||||
compatible = "xlnx,zynq-spi-r1p6";
|
||||
reg = <0xe0007000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 49 4>;
|
||||
clocks = <&clkc 26>, <&clkc 35>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
qspi: spi@e000d000 {
|
||||
clock-names = "ref_clk", "pclk";
|
||||
clocks = <&clkc 10>, <&clkc 43>;
|
||||
compatible = "xlnx,zynq-qspi-1.0";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 19 4>;
|
||||
reg = <0xe000d000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
smcc: memory-controller@e000e000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
clock-names = "memclk", "apb_pclk";
|
||||
clocks = <&clkc 11>, <&clkc 44>;
|
||||
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 18 4>;
|
||||
ranges ;
|
||||
reg = <0xe000e000 0x1000>;
|
||||
nand0: flash@e1000000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl353-nand-r2p1";
|
||||
reg = <0xe1000000 0x1000000>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
};
|
||||
nor0: flash@e2000000 {
|
||||
status = "disabled";
|
||||
compatible = "cfi-flash";
|
||||
reg = <0xe2000000 0x2000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gem0: ethernet@e000b000 {
|
||||
compatible = "cdns,zynq-gem", "cdns,gem";
|
||||
reg = <0xe000b000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <0 22 4>;
|
||||
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gem1: ethernet@e000c000 {
|
||||
compatible = "cdns,zynq-gem", "cdns,gem";
|
||||
reg = <0xe000c000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <0 45 4>;
|
||||
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
sdhci0: mmc@e0100000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&clkc 21>, <&clkc 32>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 24 4>;
|
||||
reg = <0xe0100000 0x1000>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@e0101000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&clkc 22>, <&clkc 33>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 47 4>;
|
||||
reg = <0xe0101000 0x1000>;
|
||||
};
|
||||
|
||||
slcr: slcr@f8000000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
|
||||
reg = <0xF8000000 0x1000>;
|
||||
ranges;
|
||||
clkc: clkc@100 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,ps7-clkc";
|
||||
fclk-enable = <0xf>;
|
||||
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
|
||||
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
|
||||
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
|
||||
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
|
||||
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
|
||||
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
|
||||
"gem1_aper", "sdio0_aper", "sdio1_aper",
|
||||
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
|
||||
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
|
||||
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
|
||||
"dbg_trc", "dbg_apb";
|
||||
reg = <0x100 0x100>;
|
||||
};
|
||||
|
||||
rstc: rstc@200 {
|
||||
compatible = "xlnx,zynq-reset";
|
||||
reg = <0x200 0x48>;
|
||||
#reset-cells = <1>;
|
||||
syscon = <&slcr>;
|
||||
};
|
||||
|
||||
pinctrl0: pinctrl@700 {
|
||||
compatible = "xlnx,pinctrl-zynq";
|
||||
reg = <0x700 0x200>;
|
||||
syscon = <&slcr>;
|
||||
};
|
||||
};
|
||||
|
||||
dmac_s: dmac@f8003000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0xf8003000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
|
||||
"dma4", "dma5", "dma6", "dma7";
|
||||
interrupts = <0 13 4>,
|
||||
<0 14 4>, <0 15 4>,
|
||||
<0 16 4>, <0 17 4>,
|
||||
<0 40 4>, <0 41 4>,
|
||||
<0 42 4>, <0 43 4>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <4>;
|
||||
clocks = <&clkc 27>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
devcfg: devcfg@f8007000 {
|
||||
compatible = "xlnx,zynq-devcfg-1.0";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 8 4>;
|
||||
reg = <0xf8007000 0x100>;
|
||||
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
|
||||
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
|
||||
syscon = <&slcr>;
|
||||
};
|
||||
|
||||
efuse: efuse@f800d000 {
|
||||
compatible = "xlnx,zynq-efuse";
|
||||
reg = <0xf800d000 0x20>;
|
||||
};
|
||||
|
||||
global_timer: timer@f8f00200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xf8f00200 0x20>;
|
||||
interrupts = <1 11 0x301>;
|
||||
interrupt-parent = <&intc>;
|
||||
clocks = <&clkc 4>;
|
||||
};
|
||||
|
||||
ttc0: timer@f8001000 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
|
||||
compatible = "cdns,ttc";
|
||||
clocks = <&clkc 6>;
|
||||
reg = <0xF8001000 0x1000>;
|
||||
};
|
||||
|
||||
ttc1: timer@f8002000 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
|
||||
compatible = "cdns,ttc";
|
||||
clocks = <&clkc 6>;
|
||||
reg = <0xF8002000 0x1000>;
|
||||
};
|
||||
|
||||
scutimer: timer@f8f00600 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <1 13 0x301>;
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xf8f00600 0x20>;
|
||||
clocks = <&clkc 4>;
|
||||
};
|
||||
|
||||
usb0: usb@e0002000 {
|
||||
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 28>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 21 4>;
|
||||
reg = <0xe0002000 0x1000>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
usb1: usb@e0003000 {
|
||||
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 29>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 44 4>;
|
||||
reg = <0xe0003000 0x1000>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
watchdog0: watchdog@f8005000 {
|
||||
clocks = <&clkc 45>;
|
||||
compatible = "cdns,wdt-r1p2";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 9 1>;
|
||||
reg = <0xf8005000 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
|
||||
etb@f8801000 {
|
||||
compatible = "arm,coresight-etb10", "arm,primecell";
|
||||
reg = <0xf8801000 0x1000>;
|
||||
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
in-ports {
|
||||
port {
|
||||
etb_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@f8803000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0xf8803000 0x1000>;
|
||||
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
in-ports {
|
||||
port {
|
||||
tpiu_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@f8804000 {
|
||||
compatible = "arm,coresight-static-funnel", "arm,primecell";
|
||||
reg = <0xf8804000 0x1000>;
|
||||
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
|
||||
/* funnel output ports */
|
||||
out-ports {
|
||||
port {
|
||||
funnel_out_port: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* funnel input ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel0_in_port0: endpoint {
|
||||
remote-endpoint = <&ptm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel0_in_port1: endpoint {
|
||||
remote-endpoint = <&ptm1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel0_in_port2: endpoint {
|
||||
};
|
||||
};
|
||||
/* The other input ports are not connect to anything */
|
||||
};
|
||||
};
|
||||
|
||||
ptm@f889c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0xf889c000 0x1000>;
|
||||
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
cpu = <&cpu0>;
|
||||
out-ports {
|
||||
port {
|
||||
ptm0_out_port: endpoint {
|
||||
remote-endpoint = <&funnel0_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptm@f889d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0xf889d000 0x1000>;
|
||||
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
cpu = <&cpu1>;
|
||||
out-ports {
|
||||
port {
|
||||
ptm1_out_port: endpoint {
|
||||
remote-endpoint = <&funnel0_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
263
examples/zynq7000/SW/devicetree/zynq-pl-remoteport.dtsi
Normal file
263
examples/zynq7000/SW/devicetree/zynq-pl-remoteport.dtsi
Normal file
@ -0,0 +1,263 @@
|
||||
/*
|
||||
* Zynq 7000 PL Interface over Remote-port.
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the <organization> nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
&slcr {
|
||||
/* In QEMU, the SLCR exports GPIOS (e.g the FPGA Resets). */
|
||||
#gpio-cells = <1>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* Append stuff to the PS nodes. */
|
||||
/ {
|
||||
/* This version of the AMBA PL describes the PS/PL interface
|
||||
* and not the devices that are available on the PL side.
|
||||
*
|
||||
* This is what QEMU will use to instantiate the RemotePort
|
||||
* connections allowing for cosimulation.
|
||||
*/
|
||||
amba_pl {
|
||||
cosim_rp_0: cosim@0 {
|
||||
compatible = "remote-port";
|
||||
sync = <1>;
|
||||
chrdev-id = "pl-rp";
|
||||
};
|
||||
|
||||
m_axi_gp0: rp_m_axi_gp0@40000000 {
|
||||
compatible = "remote-port-memory-master";
|
||||
remote-ports = < &cosim_rp_0 7 >;
|
||||
reg = < 0x40000000 0x40000000 >;
|
||||
};
|
||||
|
||||
m_axi_gp1: rp_m_axi_gp1@80000000 {
|
||||
compatible = "remote-port-memory-master";
|
||||
remote-ports = < &cosim_rp_0 8 >;
|
||||
reg = < 0x80000000 0x40000000 >;
|
||||
};
|
||||
|
||||
s_axi_gp0: rp_s_axi_gp0@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 0 >;
|
||||
};
|
||||
s_axi_gp1: rp_s_axi_gp1@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 1 >;
|
||||
};
|
||||
afi_0: rp_afi0@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 2 >;
|
||||
};
|
||||
afi_1: rp_afi1@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 3 >;
|
||||
};
|
||||
afi_2: rp_afi2@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 4 >;
|
||||
};
|
||||
afi_3: rp_afi3@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 5 >;
|
||||
};
|
||||
acp: rp_acp0@0 {
|
||||
compatible = "remote-port-memory-slave";
|
||||
remote-ports = < &cosim_rp_0 6 >;
|
||||
};
|
||||
|
||||
wires_in: rp_wires_in@0 {
|
||||
compatible = "remote-port-gpio";
|
||||
remote-ports = < &cosim_rp_0 9 >;
|
||||
num-gpios = < 16 >;
|
||||
/* QEMU has a bug in the interrupts-extended parsing,
|
||||
* so we need to use interrupt-parent for the moment.
|
||||
*/
|
||||
interrupt-parent = < &intc >;
|
||||
interrupts = <
|
||||
0x0 29 0x4
|
||||
0x0 30 0x4
|
||||
0x0 31 0x4
|
||||
0x0 32 0x4
|
||||
0x0 33 0x4
|
||||
0x0 34 0x4
|
||||
0x0 35 0x4
|
||||
0x0 36 0x4
|
||||
|
||||
0x0 52 0x4
|
||||
0x0 53 0x4
|
||||
0x0 54 0x4
|
||||
0x0 55 0x4
|
||||
0x0 56 0x4
|
||||
0x0 57 0x4
|
||||
0x0 58 0x4
|
||||
0x0 59 0x4
|
||||
>;
|
||||
};
|
||||
|
||||
wires_out: rp_wires_out@0 {
|
||||
compatible = "remote-port-gpio";
|
||||
remote-ports = < &cosim_rp_0 10 >;
|
||||
num-gpios = <17>;
|
||||
gpios = <
|
||||
/* 17 FPGA_OUT_RESETS. */
|
||||
&slcr 2 &slcr 3 &slcr 4 &slcr 5
|
||||
&slcr 6 &slcr 7 &slcr 8 &slcr 9
|
||||
&slcr 10 &slcr 11 &slcr 12 &slcr 13
|
||||
&slcr 14 &slcr 15 &slcr 16 &slcr 17
|
||||
&slcr 18
|
||||
>;
|
||||
};
|
||||
|
||||
rp_cosim_intr_pstopl: rp_cosim_intr_pstopl@0 {
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
compatible = "remote-port-gpio";
|
||||
remote-ports = <&cosim_rp_0 11>;
|
||||
/* There are only 28 connections but due to the offset we need
|
||||
* a higher number here.
|
||||
*/
|
||||
num-gpios = <96>;
|
||||
cell-offset-irq-num = <1>;
|
||||
};
|
||||
|
||||
/* This area can be used for implentation specific emulation*/
|
||||
rp_cosim_reserved: rp_cosim_reserved@0{
|
||||
compatible = "remote-port-memory-master";
|
||||
remote-ports = <&cosim_rp_0 12>;
|
||||
reg = <0xFE000000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 0 4>, <0 0 0 &intc 0 51 4>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 1 4>, <0 0 0 &intc 0 50 4>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 2 4>, <0 0 0 &intc 0 49 4>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 3 4>, <0 0 0 &intc 0 48 4>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 4 4>, <0 0 0 &intc 0 47 4>;
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 6 4>, <0 0 0 &intc 0 45 4>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 7 4>, <0 0 0 &intc 0 44 4>;
|
||||
};
|
||||
|
||||
&can0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 8 4>, <0 0 0 &intc 0 28 4>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 10 4>, <0 0 0 &intc 0 26 4>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 11 4>, <0 0 0 &intc 0 25 4>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 12 4>, <0 0 0 &intc 0 24 4>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 14 4>, <0 0 0 &intc 0 22 4>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 15 4>, <0 0 0 &intc 0 21 4>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 16 4>, <0 0 0 &intc 0 20 4>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 18 4>, <0 0 0 &intc 0 19 4>;
|
||||
};
|
||||
|
||||
&smcc {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 19 4>, <0 0 0 &intc 0 18 4>;
|
||||
};
|
||||
|
||||
&dmac_s {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 &rp_cosim_intr_pstopl 0 28 4>, <0 0 0 &intc 0 13 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 20 4>, <0 0 0 &intc 0 14 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 21 4>, <0 0 0 &intc 0 15 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 22 4>, <0 0 0 &intc 0 16 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 23 4>, <0 0 0 &intc 0 17 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 24 4>, <0 0 0 &intc 0 40 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 25 4>, <0 0 0 &intc 0 41 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 26 4>, <0 0 0 &intc 0 42 4>,
|
||||
<0 0 0 &rp_cosim_intr_pstopl 0 27 4>, <0 0 0 &intc 0 43 4>;
|
||||
};
|
||||
@ -6,7 +6,7 @@
|
||||
void main(){
|
||||
cpu_disable_interrups();
|
||||
// Initialize ZYNQ Processing System
|
||||
ps7_init();
|
||||
// ps7_init();
|
||||
// Start UART
|
||||
uart_setup();
|
||||
|
||||
|
||||
@ -10,6 +10,10 @@ port = 2020
|
||||
privkey = /home/joppe/.ssh/id_rsa
|
||||
pubkey = /home/joppe/.ssh/id_rsa.pub
|
||||
|
||||
# ======================================
|
||||
# BASIC FPGA WORKFLOW
|
||||
# ======================================
|
||||
|
||||
# ######################################
|
||||
# ISE IP block generation
|
||||
[target.ip]
|
||||
@ -92,10 +96,14 @@ files_verilog = OUT/synth/impl_netlist.v
|
||||
files_other = OUT/synth/impl_netlist.sdf
|
||||
# ######################################
|
||||
|
||||
# ======================================
|
||||
# PS/PL workflow
|
||||
# ======================================
|
||||
|
||||
# ######################################
|
||||
# Firmware compilation
|
||||
[target.firmware]
|
||||
toolchain = gccmake
|
||||
toolchain = make
|
||||
|
||||
# Toolchain settings
|
||||
output_files = build/app.elf DISASS
|
||||
@ -114,4 +122,42 @@ files_other = SW/linker.ld
|
||||
SW/src/zynq.h
|
||||
OUT/ip/zynqps/ps7_init.c
|
||||
OUT/ip/zynqps/ps7_init.h
|
||||
# ######################################
|
||||
|
||||
|
||||
# ######################################
|
||||
# Firmware simulation
|
||||
[target.firmsim]
|
||||
toolchain = qemu
|
||||
|
||||
# Toolchain settings
|
||||
arch = arm
|
||||
machine = xilinx-zynq-a9
|
||||
ram = 256M
|
||||
extra_opts = -serial /dev/null -serial mon:stdio
|
||||
|
||||
# Fileset
|
||||
files_executable = OUT/firmware/app.elf
|
||||
# ######################################
|
||||
|
||||
# ######################################
|
||||
# Device tree compilation
|
||||
[target.devtree]
|
||||
toolchain = make
|
||||
|
||||
# Toolchain settings
|
||||
output_files = system.dtb system.dts
|
||||
buildroot = SW/devicetree
|
||||
|
||||
# Fileset
|
||||
files_makefile = SW/devicetree/Makefile
|
||||
files_other = SW/devicetree/pcw.dtsi
|
||||
SW/devicetree/pl.dtsi
|
||||
SW/devicetree/skeleton.dtsi
|
||||
SW/devicetree/system-top.dts
|
||||
SW/devicetree/zynq-7000.dtsi
|
||||
SW/devicetree/zynq-pl-remoteport.dtsi
|
||||
SW/devicetree/include/dt-bindings/clock/xlnx-versal-clk.h
|
||||
SW/devicetree/include/dt-bindings/power/xlnx-versal-power.h
|
||||
SW/devicetree/include/dt-bindings/reset/xlnx-versal-resets.h
|
||||
# ######################################
|
||||
Reference in New Issue
Block a user