Vivado output generation

Signed-off-by: Joppe Blondel <joppe@blondel.nl>
2022-09-05 15:27:41 +02:00
parent b8267303a2
commit c1b3d252ff
7 changed files with 147 additions and 11 deletions
--- a/examples/zynq7000/RTL/toplevel.vhd
+++ b/examples/zynq7000/RTL/toplevel.vhd
@ -34,7 +34,7 @@ architecture structural of toplevel is
    -- ----------
    -- COMPONENTS
    -- ----------
-    component zynq_ps
+    component zynqps
        port (
            FCLK_CLK0         : out std_logic;
            FCLK_RESET0_N     : out std_logic;
@ -101,7 +101,7 @@ begin
        ARESETN => ARESETN(0),
        LED     => LED
    );
-    zynq_ps_i : component zynq_ps port map(
+    zynqps_i : component zynqps port map(
        -- MIO
        MIO => MIO,
        -- CLOCKS