Vivado output generation

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/zynq7000/RTL/toplevel.vhd

@@ -34,7 +34,7 @@ architecture structural of toplevel is
     -- ----------
     -- COMPONENTS
     -- ----------
-    component zynq_ps
+    component zynqps
         port (
             FCLK_CLK0         : out std_logic;
             FCLK_RESET0_N     : out std_logic;
@@ -101,7 +101,7 @@ begin
         ARESETN => ARESETN(0),
         LED     => LED
     );
-    zynq_ps_i : component zynq_ps port map(
+    zynqps_i : component zynqps port map(
         -- MIO
         MIO => MIO,
         -- CLOCKS

examples/zynq7000/project.cfg

@@ -40,7 +40,10 @@ speedgrade          = -2
 toplevel            = toplevel
 # Created netlist toplevel
 netlist_top         = toplevel
-#synth_opts         =
+synth_opts          = -flatten_hierarchy none -keep_equivalent_registers
+#opt_opts           =
+#place_opts         =
+#route_opts         =
 
 # Fileset
 files_vhdl          = RTL/heartbeat.vhd RTL/toplevel.vhd