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Added vivado synth

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-05 15:08:27 +02:00
parent 15d072bbb7
commit b8267303a2
84 changed files with 212152 additions and 2 deletions
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25
examples/zynq7000/project.cfg
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@ -22,7 +22,30 @@ package = clg400
speedgrade = -2
# Fileset
files_tcl = IP/zynqps.tcl
files_tcl = IP/zynqps.tcl IP/rst_gen.tcl
# Note: IP file names must be the same as the component name in the tcl file!
# ######################################
# ######################################
# Basic synthesis
[target.synth]
toolchain = VIVADO
# Toolchain settings
family = zynq
device = xc7z010
package = clg400
speedgrade = -2
toplevel = toplevel
# Created netlist toplevel
netlist_top = toplevel
#synth_opts =
# Fileset
files_vhdl = RTL/heartbeat.vhd RTL/toplevel.vhd
#files_verilog =
#files_sysverilog =
files_con = CON/toplevel.xdc
files_xci = OUT/ip/rst_gen/rst_gen.xci OUT/ip/zynqps/zynqps.xci
# ######################################