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Added vivado synth

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-05 15:08:27 +02:00
parent 15d072bbb7
commit b8267303a2
84 changed files with 212152 additions and 2 deletions
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4
examples/zynq7000/CON/toplevel.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property PACKAGE_PIN W13 [get_ports {LED[0]}]
set_property PACKAGE_PIN W14 [get_ports {LED[1]}]

5
examples/zynq7000/IP/rst_gen.tcl Normal file
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create_ip -vlnv xilinx.com:ip:proc_sys_reset -module_name rst_gen
set_property -dict [ list \
CONFIG.C_EXT_RESET_HIGH {0} \
CONFIG.C_AUX_RESET_HIGH {0} \
] [ get_ips rst_gen ]

34
examples/zynq7000/RTL/heartbeat.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity heartbeat is
generic (
Fin : integer := 100000000;
Fout : integer := 8
);
port (
ACLK : in std_logic;
ARESETN : in std_logic;
LED : out std_logic_vector(1 downto 0)
);
end entity;
architecture structural of heartbeat is
signal iLED : std_logic_vector(1 downto 0);
begin
LED <= iLED;
process (ACLK, ARESETN)
variable cnt : integer range 0 to Fin/(2 * Fout) - 1 := 0;
begin
if ARESETN = '0' then
cnt := 0;
iLED <= "01";
elsif rising_edge(ACLK) then
if (cnt = Fin/(2 * Fout) - 1) then
cnt := 0;
iLED <= not iLED;
else
cnt := cnt + 1;
end if;
end if;
end process;
end architecture;

145
examples/zynq7000/RTL/toplevel.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity toplevel is
port (
-- DDR
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_CAS_n : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_Clk : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_DQS_p : inout std_logic_vector(3 downto 0);
DDR_ODT : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_DSTRB : inout std_logic;
DDR_WEB : inout std_logic;
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
-- FIXED IO
MIO : inout std_logic_vector(53 downto 0);
ps_clk : inout std_logic;
ps_porb : inout std_logic;
ps_srstb : inout std_logic;
-- OWN DEFINED
LED : out std_logic_vector(1 downto 0)
);
end entity;
architecture structural of toplevel is
-- ----------
-- COMPONENTS
-- ----------
component zynq_ps
port (
FCLK_CLK0 : out std_logic;
FCLK_RESET0_N : out std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_CAS_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_Clk : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_ODT : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_WEB : inout std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
PS_SRSTB : inout std_logic;
PS_CLK : inout std_logic;
PS_PORB : inout std_logic
);
end component;
component rst_gen
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
mb_debug_sys_rst : in std_logic;
dcm_locked : in std_logic;
mb_reset : out std_logic;
bus_struct_reset : out std_logic_vector(0 downto 0);
peripheral_reset : out std_logic_vector(0 downto 0);
interconnect_aresetn : out std_logic_vector(0 downto 0);
peripheral_aresetn : out std_logic_vector(0 downto 0)
);
end component;
component heartbeat is
generic (
Fin : integer := 100000000;
Fout : integer := 8
);
port (
ACLK : in std_logic;
ARESETN : in std_logic;
LED : out std_logic_vector(1 downto 0)
);
end component;
-- -------
-- SIGNALS
-- -------
signal FCLK_CLK0 : std_logic;
signal FCLK_RESET0_N : std_logic;
signal ARESETN : std_logic_vector(0 downto 0);
begin
heartbeat_i : component heartbeat generic map(
100000000,
10
) port map(
ACLK => FCLK_CLK0,
ARESETN => ARESETN(0),
LED => LED
);
zynq_ps_i : component zynq_ps port map(
-- MIO
MIO => MIO,
-- CLOCKS
FCLK_CLK0 => FCLK_CLK0,
FCLK_RESET0_N => FCLK_RESET0_N,
-- DDR
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_Clk_n => DDR_Clk_n,
DDR_Clk => DDR_Clk,
DDR_CS_n => DDR_CS_n,
DDR_DRSTB => DDR_DSTRB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_WEB => DDR_WEB,
DDR_BankAddr => DDR_BankAddr,
DDR_Addr => DDR_Addr,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS_n => DDR_DQS_n,
DDR_DQS => DDR_DQS_p,
-- PS FIXED IO
PS_SRSTB => PS_SRSTB,
PS_CLK => PS_CLK,
PS_PORB => PS_PORB
);
rst_gen_i : rst_gen port map(
slowest_sync_clk => FCLK_CLK0,
ext_reset_in => FCLK_RESET0_N,
aux_reset_in => '1',
mb_debug_sys_rst => '0',
dcm_locked => '1',
--mb_reset => mb_reset,
--bus_struct_reset => bus_struct_reset,
--peripheral_reset => peripheral_reset,
--interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => ARESETN
);
end architecture;

25
examples/zynq7000/project.cfg
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@ -22,7 +22,30 @@ package = clg400
speedgrade = -2
# Fileset
files_tcl = IP/zynqps.tcl
files_tcl = IP/zynqps.tcl IP/rst_gen.tcl
# Note: IP file names must be the same as the component name in the tcl file!
# ######################################
# ######################################
# Basic synthesis
[target.synth]
toolchain = VIVADO
# Toolchain settings
family = zynq
device = xc7z010
package = clg400
speedgrade = -2
toplevel = toplevel
# Created netlist toplevel
netlist_top = toplevel
#synth_opts =
# Fileset
files_vhdl = RTL/heartbeat.vhd RTL/toplevel.vhd
#files_verilog =
#files_sysverilog =
files_con = CON/toplevel.xdc
files_xci = OUT/ip/rst_gen/rst_gen.xci OUT/ip/zynqps/zynqps.xci
# ######################################