Added vivado synth

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/.gen/sources_1/ip/zynqps/zynqps.vho

@@ -0,0 +1,119 @@
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+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:processing_system7:5.5
+-- IP Revision: 6
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT zynqps
+  PORT (
+    FCLK_CLK0 : OUT STD_LOGIC;
+    FCLK_RESET0_N : OUT STD_LOGIC;
+    MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
+    DDR_CAS_n : INOUT STD_LOGIC;
+    DDR_CKE : INOUT STD_LOGIC;
+    DDR_Clk_n : INOUT STD_LOGIC;
+    DDR_Clk : INOUT STD_LOGIC;
+    DDR_CS_n : INOUT STD_LOGIC;
+    DDR_DRSTB : INOUT STD_LOGIC;
+    DDR_ODT : INOUT STD_LOGIC;
+    DDR_RAS_n : INOUT STD_LOGIC;
+    DDR_WEB : INOUT STD_LOGIC;
+    DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
+    DDR_VRN : INOUT STD_LOGIC;
+    DDR_VRP : INOUT STD_LOGIC;
+    DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    DDR_DQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    PS_SRSTB : INOUT STD_LOGIC;
+    PS_CLK : INOUT STD_LOGIC;
+    PS_PORB : INOUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : zynqps
+  PORT MAP (
+    FCLK_CLK0 => FCLK_CLK0,
+    FCLK_RESET0_N => FCLK_RESET0_N,
+    MIO => MIO,
+    DDR_CAS_n => DDR_CAS_n,
+    DDR_CKE => DDR_CKE,
+    DDR_Clk_n => DDR_Clk_n,
+    DDR_Clk => DDR_Clk,
+    DDR_CS_n => DDR_CS_n,
+    DDR_DRSTB => DDR_DRSTB,
+    DDR_ODT => DDR_ODT,
+    DDR_RAS_n => DDR_RAS_n,
+    DDR_WEB => DDR_WEB,
+    DDR_BankAddr => DDR_BankAddr,
+    DDR_Addr => DDR_Addr,
+    DDR_VRN => DDR_VRN,
+    DDR_VRP => DDR_VRP,
+    DDR_DM => DDR_DM,
+    DDR_DQ => DDR_DQ,
+    DDR_DQS_n => DDR_DQS_n,
+    DDR_DQS => DDR_DQS,
+    PS_SRSTB => PS_SRSTB,
+    PS_CLK => PS_CLK,
+    PS_PORB => PS_PORB
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file zynqps.vhd when simulating
+-- the core, zynqps. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+