Added vivado synth

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/.gen/sources_1/ip/zynqps/sim/zynqps_stub.sv

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+
+//------------------------------------------------------------------------------------
+// Filename:    zynqps_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module zynqps (
+  output bit_as_bool FCLK_CLK0,
+  output bit_as_bool FCLK_RESET0_N,
+  output bit [53 : 0] MIO,
+  output bit_as_bool DDR_CAS_n,
+  output bit_as_bool DDR_CKE,
+  output bit_as_bool DDR_Clk_n,
+  output bit_as_bool DDR_Clk,
+  output bit_as_bool DDR_CS_n,
+  output bit_as_bool DDR_DRSTB,
+  output bit_as_bool DDR_ODT,
+  output bit_as_bool DDR_RAS_n,
+  output bit_as_bool DDR_WEB,
+  output bit [2 : 0] DDR_BankAddr,
+  output bit [14 : 0] DDR_Addr,
+  output bit_as_bool DDR_VRN,
+  output bit_as_bool DDR_VRP,
+  output bit [3 : 0] DDR_DM,
+  output bit [31 : 0] DDR_DQ,
+  output bit [3 : 0] DDR_DQS_n,
+  output bit [3 : 0] DDR_DQS,
+  output bit_as_bool PS_SRSTB,
+  output bit_as_bool PS_CLK,
+  output bit_as_bool PS_PORB
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module zynqps (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
+(* integer foreign = "SystemC";
+*);
+  output wire FCLK_CLK0;
+  output wire FCLK_RESET0_N;
+  inout wire [53 : 0] MIO;
+  inout wire DDR_CAS_n;
+  inout wire DDR_CKE;
+  inout wire DDR_Clk_n;
+  inout wire DDR_Clk;
+  inout wire DDR_CS_n;
+  inout wire DDR_DRSTB;
+  inout wire DDR_ODT;
+  inout wire DDR_RAS_n;
+  inout wire DDR_WEB;
+  inout wire [2 : 0] DDR_BankAddr;
+  inout wire [14 : 0] DDR_Addr;
+  inout wire DDR_VRN;
+  inout wire DDR_VRP;
+  inout wire [3 : 0] DDR_DM;
+  inout wire [31 : 0] DDR_DQ;
+  inout wire [3 : 0] DDR_DQS_n;
+  inout wire [3 : 0] DDR_DQS;
+  inout wire PS_SRSTB;
+  inout wire PS_CLK;
+  inout wire PS_PORB;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module zynqps (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
+  output wire FCLK_CLK0;
+  output wire FCLK_RESET0_N;
+  inout wire [53 : 0] MIO;
+  inout wire DDR_CAS_n;
+  inout wire DDR_CKE;
+  inout wire DDR_Clk_n;
+  inout wire DDR_Clk;
+  inout wire DDR_CS_n;
+  inout wire DDR_DRSTB;
+  inout wire DDR_ODT;
+  inout wire DDR_RAS_n;
+  inout wire DDR_WEB;
+  inout wire [2 : 0] DDR_BankAddr;
+  inout wire [14 : 0] DDR_Addr;
+  inout wire DDR_VRN;
+  inout wire DDR_VRP;
+  inout wire [3 : 0] DDR_DM;
+  inout wire [31 : 0] DDR_DQ;
+  inout wire [3 : 0] DDR_DQS_n;
+  inout wire [3 : 0] DDR_DQS;
+  inout wire PS_SRSTB;
+  inout wire PS_CLK;
+  inout wire PS_PORB;
+endmodule
+`endif