Added vivado synth

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/.gen/sources_1/ip/rst_gen/sim/rst_gen.vhd

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+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
+-- IP Revision: 13
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY proc_sys_reset_v5_0_13;
+USE proc_sys_reset_v5_0_13.proc_sys_reset;
+
+ENTITY rst_gen IS
+  PORT (
+    slowest_sync_clk : IN STD_LOGIC;
+    ext_reset_in : IN STD_LOGIC;
+    aux_reset_in : IN STD_LOGIC;
+    mb_debug_sys_rst : IN STD_LOGIC;
+    dcm_locked : IN STD_LOGIC;
+    mb_reset : OUT STD_LOGIC;
+    bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END rst_gen;
+
+ARCHITECTURE rst_gen_arch OF rst_gen IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF rst_gen_arch: ARCHITECTURE IS "yes";
+  COMPONENT proc_sys_reset IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_EXT_RST_WIDTH : INTEGER;
+      C_AUX_RST_WIDTH : INTEGER;
+      C_EXT_RESET_HIGH : STD_LOGIC;
+      C_AUX_RESET_HIGH : STD_LOGIC;
+      C_NUM_BUS_RST : INTEGER;
+      C_NUM_PERP_RST : INTEGER;
+      C_NUM_INTERCONNECT_ARESETN : INTEGER;
+      C_NUM_PERP_ARESETN : INTEGER
+    );
+    PORT (
+      slowest_sync_clk : IN STD_LOGIC;
+      ext_reset_in : IN STD_LOGIC;
+      aux_reset_in : IN STD_LOGIC;
+      mb_debug_sys_rst : IN STD_LOGIC;
+      dcm_locked : IN STD_LOGIC;
+      mb_reset : OUT STD_LOGIC;
+      bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+    );
+  END COMPONENT proc_sys_reset;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
+BEGIN
+  U0 : proc_sys_reset
+    GENERIC MAP (
+      C_FAMILY => "zynq",
+      C_EXT_RST_WIDTH => 4,
+      C_AUX_RST_WIDTH => 4,
+      C_EXT_RESET_HIGH => '0',
+      C_AUX_RESET_HIGH => '0',
+      C_NUM_BUS_RST => 1,
+      C_NUM_PERP_RST => 1,
+      C_NUM_INTERCONNECT_ARESETN => 1,
+      C_NUM_PERP_ARESETN => 1
+    )
+    PORT MAP (
+      slowest_sync_clk => slowest_sync_clk,
+      ext_reset_in => ext_reset_in,
+      aux_reset_in => aux_reset_in,
+      mb_debug_sys_rst => mb_debug_sys_rst,
+      dcm_locked => dcm_locked,
+      mb_reset => mb_reset,
+      bus_struct_reset => bus_struct_reset,
+      peripheral_reset => peripheral_reset,
+      interconnect_aresetn => interconnect_aresetn,
+      peripheral_aresetn => peripheral_aresetn
+    );
+END rst_gen_arch;