Added vivado synth

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/.gen/sources_1/ip/rst_gen/doc/proc_sys_reset_v5_0_changelog.txt

@@ -0,0 +1,238 @@
+2021.2:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2021.1.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2021.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2020.3:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2020.2.2:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2020.2.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2020.2:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2020.1.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2020.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.2.2:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.2.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.2:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.1.3:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.1.2:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.1.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2019.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2018.3.1:
+ * Version 5.0 (Rev. 13)
+ * No changes
+
+2018.3:
+ * Version 5.0 (Rev. 13)
+ * General: removed equivalent_register_removal
+
+2018.2:
+ * Version 5.0 (Rev. 12)
+ * No changes
+
+2018.1:
+ * Version 5.0 (Rev. 12)
+ * No changes
+
+2017.4:
+ * Version 5.0 (Rev. 12)
+ * No changes
+
+2017.3:
+ * Version 5.0 (Rev. 12)
+ * General: Reset outputs initialized with a POR value
+
+2017.2:
+ * Version 5.0 (Rev. 11)
+ * No changes
+
+2017.1:
+ * Version 5.0 (Rev. 11)
+ * General: Board flow related updates, no functional changes
+
+2016.4:
+ * Version 5.0 (Rev. 10)
+ * No changes
+
+2016.3:
+ * Version 5.0 (Rev. 10)
+ * General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+
+2016.2:
+ * Version 5.0 (Rev. 9)
+ * No changes
+
+2016.1:
+ * Version 5.0 (Rev. 9)
+ * Updated bd.tcl post config procedure. No functional change.
+
+2015.4.2:
+ * Version 5.0 (Rev. 8)
+ * No changes
+
+2015.4.1:
+ * Version 5.0 (Rev. 8)
+ * No changes
+
+2015.4:
+ * Version 5.0 (Rev. 8)
+ * No changes
+
+2015.3:
+ * Version 5.0 (Rev. 8)
+ * Renamed the internal module to avoid conflict with VHDL2008 keyword, no functional change.
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Revision change in one or more subcores
+
+2015.2.1:
+ * Version 5.0 (Rev. 7)
+ * No changes
+
+2015.2:
+ * Version 5.0 (Rev. 7)
+ * No changes
+
+2015.1:
+ * Version 5.0 (Rev. 7)
+ * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.0 (Rev. 6)
+ * No changes
+
+2014.4:
+ * Version 5.0 (Rev. 6)
+ * No changes
+
+2014.3:
+ * Version 5.0 (Rev. 6)
+ * Modified to use new sub-cores in place of proc_common,no functional changes
+ * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
+ * Updated core to use utils.tcl, needed for board flow from common location
+
+2014.2:
+ * Version 5.0 (Rev. 5)
+ * Enhanced support for IP Integrator
+ * Board flow related updates, no functional changes
+
+2014.1:
+ * Version 5.0 (Rev. 4)
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.0 (Rev. 3)
+ * Added exdes.xdc file
+ * Changed the associated resets for slowest_sync_clk
+ * Kintex UltraScale Pre-Production support
+
+2013.3:
+ * Version 5.0 (Rev. 2)
+ * Changed board flow specific parameter name as per new requirements
+ * Added example design and demonstration testbench
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
+ * Support for 7-series devices at Production status
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Added BETA support for future devices.
+ * No other RTL updates
+
+2013.1:
+ * Version 5.0
+ * Updated version for 2013.1
+ * Updated bd.tcl for board flow
+ * No other RTL updates
+
+(c) Copyright 2013 - 2021 Xilinx, Inc. All rights reserved.
+
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+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
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