From af52ee65fa84e75b3444da988d6e86f184c8dea0 Mon Sep 17 00:00:00 2001 From: Joppe Blondel Date: Sat, 3 Sep 2022 15:40:43 +0200 Subject: [PATCH] Added spartan 6 example Signed-off-by: Joppe Blondel --- examples/spartan6/.gitignore | 2 + examples/spartan6/CON/toplevel.ucf | 41 +++++++++++++++++++ examples/spartan6/README.md | 5 +++ examples/spartan6/RTL/toplevel.vhd | 28 +++++++++++++ examples/spartan6/SIM/tb_toplevel.vhd | 49 ++++++++++++++++++++++ examples/spartan6/project.cfg | 58 +++++++++++++++++++++++++++ scripts/remotesyn | 3 +- 7 files changed, 185 insertions(+), 1 deletion(-) create mode 100644 examples/spartan6/.gitignore create mode 100644 examples/spartan6/CON/toplevel.ucf create mode 100644 examples/spartan6/README.md create mode 100644 examples/spartan6/RTL/toplevel.vhd create mode 100644 examples/spartan6/SIM/tb_toplevel.vhd create mode 100644 examples/spartan6/project.cfg diff --git a/examples/spartan6/.gitignore b/examples/spartan6/.gitignore new file mode 100644 index 0000000..3e721d6 --- /dev/null +++ b/examples/spartan6/.gitignore @@ -0,0 +1,2 @@ +OUT +.build \ No newline at end of file diff --git a/examples/spartan6/CON/toplevel.ucf b/examples/spartan6/CON/toplevel.ucf new file mode 100644 index 0000000..ddf2525 --- /dev/null +++ b/examples/spartan6/CON/toplevel.ucf @@ -0,0 +1,41 @@ +NET "ACLK" LOC = P126; +NET "ACLK" TNM_NET = "SYS_CLK_PIN"; +TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %; + +NET "LED[0]" LOC = P119; +NET "LED[0]" IOSTANDARD = LVCMOS33; +NET "LED[0]" DRIVE = 8; +NET "LED[1]" LOC = P118; +NET "LED[1]" IOSTANDARD = LVCMOS33; +NET "LED[1]" DRIVE = 8; +NET "LED[2]" LOC = P117; +NET "LED[2]" IOSTANDARD = LVCMOS33; +NET "LED[2]" DRIVE = 8; +NET "LED[3]" LOC = P116; +NET "LED[3]" IOSTANDARD = LVCMOS33; +NET "LED[3]" DRIVE = 8; +NET "LED[4]" LOC = P115; +NET "LED[4]" IOSTANDARD = LVCMOS33; +NET "LED[4]" DRIVE = 8; +NET "LED[5]" LOC = P114; +NET "LED[5]" IOSTANDARD = LVCMOS33; +NET "LED[5]" DRIVE = 8; +NET "LED[6]" LOC = P112; +NET "LED[6]" IOSTANDARD = LVCMOS33; +NET "LED[6]" DRIVE = 8; +NET "LED[7]" LOC = P111; +NET "LED[7]" IOSTANDARD = LVCMOS33; +NET "LED[7]" DRIVE = 8; + +NET "SW[0]" LOC = P124; +NET "SW[0]" IOSTANDARD = LVCMOS33; +NET "SW[0]" PULLUP; +NET "SW[1]" LOC = P123; +NET "SW[1]" IOSTANDARD = LVCMOS33; +NET "SW[1]" PULLUP; +NET "SW[2]" LOC = P121; +NET "SW[2]" IOSTANDARD = LVCMOS33; +NET "SW[2]" PULLUP; +NET "SW[3]" LOC = P120; +NET "SW[3]" IOSTANDARD = LVCMOS33; +NET "SW[3]" PULLUP; \ No newline at end of file diff --git a/examples/spartan6/README.md b/examples/spartan6/README.md new file mode 100644 index 0000000..0bba9eb --- /dev/null +++ b/examples/spartan6/README.md @@ -0,0 +1,5 @@ +# Spartan 6 example + +Run full toolchain: `remotesyn -l all total` +Run simulation: `remotesyn -l sim presim_total` +Run post-simulation (after synthesis and implementation): `remotesyn -l sim postsim_total` \ No newline at end of file diff --git a/examples/spartan6/RTL/toplevel.vhd b/examples/spartan6/RTL/toplevel.vhd new file mode 100644 index 0000000..e654e57 --- /dev/null +++ b/examples/spartan6/RTL/toplevel.vhd @@ -0,0 +1,28 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity toplevel is + port ( + ACLK : in std_logic; + LED : out std_logic_vector(7 downto 0); + SW : in std_logic_vector(3 downto 0) + ); +end toplevel; + +architecture structural of toplevel is + signal ARESETN : std_logic; +begin + + ARESETN <= SW(3); + + process(ACLK, ARESETN) + begin + if ARESETN='0' then + LED <= "11111111"; + elsif rising_edge(ACLK) then + LED <= SW & SW; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/examples/spartan6/SIM/tb_toplevel.vhd b/examples/spartan6/SIM/tb_toplevel.vhd new file mode 100644 index 0000000..2c3b153 --- /dev/null +++ b/examples/spartan6/SIM/tb_toplevel.vhd @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity tb_toplevel is +end entity; + +architecture behavioural of tb_toplevel is + + -- COMPONENTS + -- ---------- + component toplevel is + port ( + ACLK : in std_logic; + LED : out std_logic_vector(7 downto 0); + SW : in std_logic_vector(3 downto 0) + ); + end component; + + -- SIGNALS + -- ------- + signal ACLK : std_logic := '0'; + signal LED : std_logic_vector(7 downto 0) := "00000000"; + signal SW : std_logic_vector(3 downto 0) := "0111"; + +begin + + c_toplevel : component toplevel port map( + ACLK, LED, SW + ); + + ACLK <= not ACLK after 10 ns; + SW(3) <= '1' after 150 ns; + + process + begin + wait until SW(3)='1'; + + SW(2 downto 0) <= "101"; + wait for 75 ns; + SW(2 downto 0) <= "010"; + wait for 19 ns; + SW(2 downto 0) <= "111"; + + wait for 100 ns; + report "END OF SIMULATION" severity failure; + end process; + +end architecture; \ No newline at end of file diff --git a/examples/spartan6/project.cfg b/examples/spartan6/project.cfg new file mode 100644 index 0000000..f836737 --- /dev/null +++ b/examples/spartan6/project.cfg @@ -0,0 +1,58 @@ +# PROJECT SETTINGS +# ---------------- +[server] +hostname = localhost +port = 8080 +privkey = keys/id_rsa +pubkey = keys/id_rsa.pub + +[project] +# Toolchain selection. choose between [ISE, VIVADO] +toolchain = ISE +out_dir = OUT + +[target] +family = spartan6 +device = xc6slx9 +package = tqg144 +speedgrade = -2 + +# HARDWARE TARGETS +# ---------------- +[total] +src_vhdl = RTL/toplevel.vhd +src_verilog = +src_sysverilog = +src_constraints = CON/toplevel.ucf +src_ip = +toplevel = toplevel +extra_options = xst -glob_opt max_delay -opt_mode speed + netgen -ism + map -ol high -xe n + par -ol high -xe n + trce -v 3 -s 2 -n 3 -fastpaths + +# SIMULATION TARGETS +# ------------------ +[presim_total] +simtype = presim +src_vhdl = RTL/toplevel.vhd + SIM/tb_toplevel.vhd +src_verilog = +src_sysverilog = +toplevel = tb_toplevel +runtime = all +levels = 10 + +[postsim_total] +simtype = postsim +src_vhdl = SIM/tb_toplevel.vhd +src_verilog = OUT/total/total.map.v +src_sysverilog = +src_ip = +src_sdf = OUT/total/total.map.sdf +toplevel = tb_toplevel +runtime = all +delay = max +sdfroot = /tb_toplevel/c_toplevel +levels = 10 \ No newline at end of file diff --git a/scripts/remotesyn b/scripts/remotesyn index 77765c5..4dae194 100644 --- a/scripts/remotesyn +++ b/scripts/remotesyn @@ -202,9 +202,10 @@ if __name__=="__main__": f.write("# ----------------\n") f.write("[server]\nhostname = localhost\nport = 8080\nprivkey = keys/id_rsa\npubkey = keys/id_rsa.pub\n\n") f.write("[project]\n# Toolchain selection. choose between [ISE, VIVADO]\ntoolchain = ISE\nout_dir = OUT\n\n") - f.write("[target]\nfamily = spartan6\ndevice = xc6lsx9\npackage = tgq144\nspeedgrade = -2\n\n") + f.write("[target]\nfamily = spartan6\ndevice = xc6slx9\npackage = tqg144\nspeedgrade = -2\n\n") f.write("# HARDWARE TARGETS\n") f.write("# ----------------\n") + f.write("[total]\n") f.write("src_vhdl = RTL/toplevel.vhd\nsrc_verilog = \nsrc_sysverilog = \n") f.write("src_constraints = CON/toplevel.ucf\nsrc_ip = \ntoplevel = toplevel\nextra_options = ") exit(1)