First version of zynq cosimulation added

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/zynq7000/project.cfg

@@ -160,4 +160,43 @@ files_other         = SW/devicetree/pcw.dtsi
                       SW/devicetree/include/dt-bindings/clock/xlnx-versal-clk.h
                       SW/devicetree/include/dt-bindings/power/xlnx-versal-power.h
                       SW/devicetree/include/dt-bindings/reset/xlnx-versal-resets.h
+# ######################################
+
+# ######################################
+# Hardware-firmware cosimulation PS part
+[target.cosim_ps]
+toolchain           = qemu
+
+# Toolchain settings
+arch                = xilinxarm
+machine             = arm-generic-fdt-7series
+ram                 = 256M
+extra_opts          = -serial /dev/null -serial mon:stdio -dtb ../OUT/devtree/system.dtb \
+                      -machine-path /tmp \
+                      -icount 1 -sync-quantum 100000 \
+                      -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4
+
+# Fileset
+files_executable    = OUT/firmware/app.elf
+files_other         = OUT/devtree/system.dtb
+# ######################################
+
+# ######################################
+# Hardware-firmware cosimulation PL part
+# Note: currently not using xsim since compilation with xilinx 
+# provided tools are horrible on linux
+[target.cosim_pl]
+toolchain           = questa
+
+# Toolchain settings
+toplevel            = tb_cosim
+vcdlevels           = 20
+runtime             = all
+
+# Fileset
+files_vhdl          = RTL/heartbeat.vhd
+# files_verilog      =
+files_sysverilog    = SIM/tb_cosim.sv
+files_c             = SIM/c/remote-port-proto.c SIM/c/cosim.c
+files_other         = SIM/c/remote-port-proto.h
 # ######################################