Added base GOWIN eda script
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2
examples/GW1NSR-4C/.gitignore
vendored
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2
examples/GW1NSR-4C/.gitignore
vendored
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OUT
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BUILD
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8
examples/GW1NSR-4C/CON/io.cst
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examples/GW1NSR-4C/CON/io.cst
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IO_LOC "led_o" 10;
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IO_PORT "led_o" PULL_MODE=NONE DRIVE=8;
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IO_LOC "reset_n_i" 15;
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IO_PORT "reset_n_i" PULL_MODE=UP;
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IO_LOC "clk_i" 45;
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IO_PORT "clk_i" PULL_MODE=UP;
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1
examples/GW1NSR-4C/CON/io.sdc
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1
examples/GW1NSR-4C/CON/io.sdc
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create_clock -name CLK_IN -period 37.037 -waveform {0 18.52} [get_ports {clk_i}]
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23
examples/GW1NSR-4C/RTL/toplevel.v
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23
examples/GW1NSR-4C/RTL/toplevel.v
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module led_blink
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(
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input clk_i,
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input reset_n_i,
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output led_o
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);
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reg [23:0] counter;
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reg polarity;
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always@(posedge clk_i) begin
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if (!reset_n_i)
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counter <= 24'h00000;
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else
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counter <= counter + 1'b1;
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if (counter == 24'hFFFFF)
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polarity <= ~polarity;
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end
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assign led_o = polarity;
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endmodule
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28
examples/GW1NSR-4C/project.cfg
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examples/GW1NSR-4C/project.cfg
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[project]
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name = gowin_project
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version = 0.1
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out_dir = OUT
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build_dir = BUILD
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[server]
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hostname = localhost
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port = 2020
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privkey = /home/joppe/.ssh/id_rsa
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pubkey = /home/joppe/.ssh/id_rsa.pub
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# ######################################
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# Basic synthesis
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[target.synth]
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toolchain = gowin
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# Toolchain settings
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family = GW1NSR-4C
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device = GW1NSR-LV4CQN48PC6/I5
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toplevel = led_blink
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# Fileset
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# files_vhdl =
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files_verilog = RTL/toplevel.v
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files_con = CON/io.cst
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CON/io.sdc
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# ######################################
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