Added new stuff to readme
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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@ -8,6 +8,9 @@ Remotesyn is a tool which proves a general abstraction for HDL/FPGA toolchains s
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+ Xilinx VIVADO synthesis and bitstream generation [`VIVADO`]
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+ Xilinx Vivado IP core generation [`VIVADO-IP`]
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+ Xilinx xsim (Vivado) simulation (pre and post synthesis) [`xsim`]
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+ Makefile build [`make`]
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+ QEMU simulation (nographic mode) [`qemu`]
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+ QuestaSim simulation [`questa`]
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The HDL project is configured with a config file (in ini format) and should provide execution targets specified by a `[target.<target_name>]` tag with a toolchain setting (see the example directory for examples).
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