21
LICENCE
Normal file
21
LICENCE
Normal file
@ -0,0 +1,21 @@
|
|||||||
|
Copyright (c) 2022, Joppe Blondel
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||||
|
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||||
|
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
8
examples/spartan6/IP/blk_mem.xco
Normal file
8
examples/spartan6/IP/blk_mem.xco
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
SELECT blk_mem xilinx.com:ip:blk_mem_gen:7.3
|
||||||
|
CSET component_name = blk_mem
|
||||||
|
CSET interface_type = Native
|
||||||
|
CSET port_a_clock = 100
|
||||||
|
CSET read_width_a = 32
|
||||||
|
CSET write_width_a = 32
|
||||||
|
CSET write_depth_a = 256
|
||||||
|
GENERATE
|
@ -10,6 +10,24 @@ port = 2020
|
|||||||
privkey = /home/joppe/.ssh/id_rsa
|
privkey = /home/joppe/.ssh/id_rsa
|
||||||
pubkey = /home/joppe/.ssh/id_rsa.pub
|
pubkey = /home/joppe/.ssh/id_rsa.pub
|
||||||
|
|
||||||
|
# ######################################
|
||||||
|
# ISE IP block generation
|
||||||
|
[target.ip]
|
||||||
|
toolchain = ISE_IP
|
||||||
|
|
||||||
|
# Toolchain settings
|
||||||
|
family = spartan6
|
||||||
|
device = xc6slx9
|
||||||
|
package = tqg144
|
||||||
|
speedgrade = -2
|
||||||
|
#coregen_opts =
|
||||||
|
|
||||||
|
# Fileset
|
||||||
|
files_xco = IP/blk_mem.xco
|
||||||
|
# Note: IP file names must be the same as the component name in the xco file!
|
||||||
|
|
||||||
|
# ######################################
|
||||||
|
|
||||||
# ######################################
|
# ######################################
|
||||||
# Basic synthesis
|
# Basic synthesis
|
||||||
[target.synth]
|
[target.synth]
|
||||||
|
@ -6,7 +6,11 @@ from .util_ISE.netgen import netgen
|
|||||||
from .util_ISE.bitgen import bitgen
|
from .util_ISE.bitgen import bitgen
|
||||||
from .util_ISE.trce import trce
|
from .util_ISE.trce import trce
|
||||||
|
|
||||||
|
import shutil
|
||||||
|
|
||||||
def do(config, target, log, subprocesses, prefix='.'):
|
def do(config, target, log, subprocesses, prefix='.'):
|
||||||
|
shutil.rmtree(config.get('project', 'build_dir', fallback='build'), True)
|
||||||
|
|
||||||
log("Syntesize:")
|
log("Syntesize:")
|
||||||
|
|
||||||
res = xst(config, target, log, subprocesses, prefix)
|
res = xst(config, target, log, subprocesses, prefix)
|
||||||
|
20
remotesyn/toolchains/ISE_IP.py
Normal file
20
remotesyn/toolchains/ISE_IP.py
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
from .util_ISE.xst import xst
|
||||||
|
from .util_ISE.ngdbuild import ngdbuild
|
||||||
|
from .util_ISE.map import map
|
||||||
|
from .util_ISE.par import par
|
||||||
|
from .util_ISE.netgen import netgen
|
||||||
|
from .util_ISE.bitgen import bitgen
|
||||||
|
from .util_ISE.trce import trce
|
||||||
|
from .util_ISE.coregen import coregen
|
||||||
|
|
||||||
|
import shutil
|
||||||
|
|
||||||
|
def do(config, target, log, subprocesses, prefix='.'):
|
||||||
|
shutil.rmtree(config.get('project', 'build_dir', fallback='build'), True)
|
||||||
|
|
||||||
|
log("Generate IP's:")
|
||||||
|
|
||||||
|
res = coregen(config, target, log, subprocesses, prefix)
|
||||||
|
if res != 0:
|
||||||
|
print("ERROR: coregen returned with", res)
|
||||||
|
return res
|
64
remotesyn/toolchains/util_ISE/coregen.py
Normal file
64
remotesyn/toolchains/util_ISE/coregen.py
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
import shutil
|
||||||
|
import os
|
||||||
|
import time
|
||||||
|
import subprocess
|
||||||
|
|
||||||
|
def coregen(config, target, log, subprocesses, prefix='.') -> int:
|
||||||
|
log(" - parsing options")
|
||||||
|
device = config.get(f'target.{target}', 'device', fallback='')
|
||||||
|
family = config.get(f'target.{target}', 'family', fallback='')
|
||||||
|
package = config.get(f'target.{target}', 'package', fallback='')
|
||||||
|
speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='')
|
||||||
|
coregen_opts = config.get(f'target.{target}', 'coregen_opts', fallback='')
|
||||||
|
files_xco = config.get(f'target.{target}', 'files_xco', fallback='').split()
|
||||||
|
build_dir = config.get(f'project', 'build_dir', fallback='build')
|
||||||
|
out_dir = config.get(f'project', 'out_dir', fallback='out')
|
||||||
|
|
||||||
|
prefix = f'{os.getcwd()}/{prefix}'
|
||||||
|
build_dir = f'{prefix}/{build_dir}'
|
||||||
|
out_dir = f'{prefix}/{out_dir}/{target}'
|
||||||
|
|
||||||
|
log(" - creating output directories")
|
||||||
|
os.makedirs(build_dir, exist_ok=True)
|
||||||
|
os.makedirs(out_dir, exist_ok=True)
|
||||||
|
|
||||||
|
res = 0
|
||||||
|
|
||||||
|
for fxco in files_xco:
|
||||||
|
cname = fxco.split('/')[-1].split('.')[0]
|
||||||
|
|
||||||
|
log(" - Generating", cname, "...")
|
||||||
|
|
||||||
|
log(" - Writing device file")
|
||||||
|
with open(f"{build_dir}/coregen_{cname}.cgp", "w") as f:
|
||||||
|
f.write(f'SET busformat = BusFormatAngleBracketNotRipped\n')
|
||||||
|
f.write(f'SET designentry = VHDL\n')
|
||||||
|
f.write(f'SET device = {device}\n')
|
||||||
|
f.write(f'SET devicefamily = {family}\n')
|
||||||
|
f.write(f'SET package = {package}\n')
|
||||||
|
f.write(f'SET speedgrade = {speedgrade}\n')
|
||||||
|
f.write(f'SET flowvendor = Other\n')
|
||||||
|
f.write(f'SET verilogsim = true\n')
|
||||||
|
f.write(f'SET vhdlsim = true\n')
|
||||||
|
|
||||||
|
log(" - run coregen")
|
||||||
|
p = subprocess.Popen(f"coregen {coregen_opts} -p coregen_{cname}.cgp -b {prefix}/{fxco}",
|
||||||
|
shell=True, cwd=build_dir,
|
||||||
|
stdin=subprocess.DEVNULL, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)
|
||||||
|
subprocesses.append(p)
|
||||||
|
while p.poll() is None:
|
||||||
|
time.sleep(1)
|
||||||
|
res = p.returncode
|
||||||
|
|
||||||
|
log(" - copy logs")
|
||||||
|
shutil.copy(f'{build_dir}/coregen.log', f'{out_dir}/coregen_{cname}.log')
|
||||||
|
|
||||||
|
if res==0:
|
||||||
|
log(" - copy output files")
|
||||||
|
shutil.copy(f'{build_dir}/{cname}.vhd', f'{out_dir}/{cname}.vhd')
|
||||||
|
shutil.copy(f'{build_dir}/{cname}.v', f'{out_dir}/{cname}.v')
|
||||||
|
# shutil.copy(f'{build_dir}/{cname}.ngc', f'{out_dir}/{cname}.ngc')
|
||||||
|
else:
|
||||||
|
return res
|
||||||
|
|
||||||
|
return res
|
Reference in New Issue
Block a user