ISE coregen added

Signed-off-by: Joppe Blondel <joppe@blondel.nl>
2022-09-05 13:55:03 +02:00
parent aa9aa6aa78
commit 1bf61807fc
6 changed files with 135 additions and 0 deletions
--- a/examples/spartan6/IP/blk_mem.xco
+++ b/examples/spartan6/IP/blk_mem.xco
@ -0,0 +1,8 @@
+SELECT blk_mem xilinx.com:ip:blk_mem_gen:7.3
+CSET component_name = blk_mem
+CSET interface_type = Native
+CSET port_a_clock = 100
+CSET read_width_a = 32
+CSET write_width_a = 32
+CSET write_depth_a = 256
+GENERATE