ISE coregen added

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/spartan6/IP/blk_mem.xco

@@ -0,0 +1,8 @@
+SELECT blk_mem xilinx.com:ip:blk_mem_gen:7.3
+CSET component_name = blk_mem
+CSET interface_type = Native
+CSET port_a_clock = 100
+CSET read_width_a = 32
+CSET write_width_a = 32
+CSET write_depth_a = 256
+GENERATE

examples/spartan6/project.cfg

@@ -10,6 +10,24 @@ port                = 2020
 privkey             = /home/joppe/.ssh/id_rsa
 pubkey              = /home/joppe/.ssh/id_rsa.pub
 
+# ######################################
+# ISE IP block generation
+[target.ip]
+toolchain           = ISE_IP
+
+# Toolchain settings
+family              = spartan6
+device              = xc6slx9
+package             = tqg144
+speedgrade          = -2
+#coregen_opts       =
+
+# Fileset
+files_xco           = IP/blk_mem.xco
+# Note: IP file names must be the same as the component name in the xco file!
+
+# ######################################
+
 # ######################################
 # Basic synthesis
 [target.synth]