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// IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
// IP Revision: 13

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
rst_gen your_instance_name (
  .slowest_sync_clk(slowest_sync_clk),          // input wire slowest_sync_clk
  .ext_reset_in(ext_reset_in),                  // input wire ext_reset_in
  .aux_reset_in(aux_reset_in),                  // input wire aux_reset_in
  .mb_debug_sys_rst(mb_debug_sys_rst),          // input wire mb_debug_sys_rst
  .dcm_locked(dcm_locked),                      // input wire dcm_locked
  .mb_reset(mb_reset),                          // output wire mb_reset
  .bus_struct_reset(bus_struct_reset),          // output wire [0 : 0] bus_struct_reset
  .peripheral_reset(peripheral_reset),          // output wire [0 : 0] peripheral_reset
  .interconnect_aresetn(interconnect_aresetn),  // output wire [0 : 0] interconnect_aresetn
  .peripheral_aresetn(peripheral_aresetn)      // output wire [0 : 0] peripheral_aresetn
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file rst_gen.v when simulating
// the core, rst_gen. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

