[project]
name                = spartan6_project
version             = 0.1
out_dir             = OUT
build_dir           = BUILD

[server]
hostname            = localhost
port                = 2020
privkey             = /home/joppe/.ssh/id_rsa
pubkey              = /home/joppe/.ssh/id_rsa.pub

# ######################################
# ISE IP block generation
[target.ip]
toolchain           = ISE_IP

# Toolchain settings
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
#coregen_opts       =

# Fileset
files_xco           = IP/blk_mem.xco
# Note: IP file names must be the same as the component name in the xco file!

# ######################################

# ######################################
# Basic synthesis
[target.synth]
toolchain           = ISE

# Toolchain settings
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
toplevel            = toplevel
#xst_opts           =
#ngdbuild_opts      =
#map_opts           =
#par_opts           =
#netgen_opts        =
#bitgen_opts        =
#trce_opts          =

# Fileset
files_vhdl          = RTL/toplevel.vhd
#files_verilog      =
files_con           = CON/toplevel.ucf
# ######################################

# ######################################
# Behavioural simulation
[target.sim]
toolchain           = isim

# Toolchain settings
toplevel            = tb_toplevel
vcdlevels           = 20
runtime             = all
#fuse_opts           =
#isim_opts           =

# Fileset
files_vhdl          = RTL/toplevel.vhd
                      SIM/tb_toplevel.vhd
#files_verilog      =
# ######################################

# ######################################
# Post synthesis simulation (synth must have ran first)
[target.psim]
toolchain           = isim

# Toolchain settings
toplevel            = tb_toplevel
vcdlevels           = 20
runtime             = all
fuse_opts           = --maxdelay work.glbl
isim_opts           = -sdfmax /tb_toplevel/c_toplevel=~D~/OUT/synth/synth.sdf
# ~D~ is replaced with the top directory of the project

# Fileset
files_vhdl          = SIM/tb_toplevel.vhd
files_verilog       = OUT/synth/synth.v
files_other         = OUT/synth/synth.sdf
# ######################################