`timescale 1ns/1ps

module toplevel_tb;
    reg clk;
    reg reset_n;
    reg button;
    wire led;

    toplevel m_toplevel(
        .clk(clk),
        .reset_n(reset_n),
        .button(button),
        .led(led)
    );

    initial begin
        $dumpfile("toplevel_tb.vcd");
        $dumpvars (0, toplevel_tb);

        clk <= 1'b0;
        reset_n <= 1'b0;
        button <= 1'b0;

        #50 reset_n <= 1'b1;

        // Wait for clk 120 starts
        @(posedge toplevel_tb.m_toplevel.clk_120);

        #78 button <= 1'b1;

        #185 button <= 1'b0;

        #400
        $finish;
    end

    always #37 clk = ~clk;

    // Simulation stuff
    // PLL quickstart
    `ifndef TIMING_SIM
    reg tb_pll_clk = 1'b0;
    always #4.15 tb_pll_clk = ~tb_pll_clk;
    initial begin
        @(posedge reset_n);
        repeat (8) @(posedge clk);      // give the model time to measure CLKIN
        force toplevel_tb.m_toplevel.m_pll.pllvr_inst.LOCK    = 1'b1;
        force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUT  = tb_pll_clk;
        force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUTP = tb_pll_clk;
    end
    `endif
    // SDF annotation
    `ifdef TIMING_SIM
    initial begin
        $sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");
    end
    `endif

endmodule