`timescale 1ns/1ps

module toplevel(
    input wire clk,
    input wire reset_n,
    input wire button,
    output wire led
);
    reg led_v;
    wire clk_120;

    gw_pllvr m_pll(
        .clkout(clk_120),
        .reset(!reset_n),
        .clkin(clk)
    );

    always @(posedge clk_120 or negedge reset_n) begin
      if (!reset_n) begin
        led_v <= 1'b0;
      end else begin
        led_v <= button;
      end
    end
    assign led = led_v;

endmodule