`timescale 1ns/1ps

// =============================================================================
// Clock generator/PLL
// Simple direct generation for simulation purposes
// =============================================================================
module clk_gen(
    input wire clk_in,
    output wire clk_out_15
);
    reg clk_15;
    initial clk_15 <= 1'b0;
    always #6.667 clk_15 <= !clk_15;
    assign clk_out_15 = clk_15;
endmodule