`timescale 1ns/1ps

module tb_serving();
    // Clock and reset generation
    reg clk;
    reg resetn;
    initial clk <= 1'b0;
    always #4.17 clk <= !clk;
    initial begin 
        resetn <= 1'b1;
        #(4.17*40) resetn <= 1'b0;
        #(4.17*40) resetn <= 1'b1;
    end;

    // Default run
    initial begin
        $dumpfile("out.vcd");
        $dumpvars;
        #50_000
        $finish;
    end;

    wire [31:0] wb_adr;
    wire [31:0] wb_dat;
    wire [3:0] wb_sel;
    wire wb_we;
    wire wb_stb;
    wire [31:0] wb_rdt;
    wire wb_ack;

    wire [31:0] GPIO;

    serving #(
        .memfile("../sw/blinky/blinky.hex"),
        .memsize(8192),
        .sim(1'b0),
        .RESET_STRATEGY("MINI"),
        .WITH_CSR(1)
    ) serv (
        .i_clk(clk),
        .i_rst(!resetn),
        .i_timer_irq(1'b0),
        .i_wb_rdt(wb_rdt),
        .i_wb_ack(wb_ack),
        .o_wb_adr(wb_adr),
        .o_wb_dat(wb_dat),
        .o_wb_sel(wb_sel),
        .o_wb_we(wb_we),
        .o_wb_stb(wb_stb)
    );

    wb_gpio #(
      .address(32'h80000000)
    ) gpio (
        .i_wb_clk(clk),
        .i_wb_dat(wb_dat),
        .i_wb_adr(wb_adr),
        .i_wb_we(wb_we),
        .i_wb_stb(wb_stb),
        .i_wb_sel(wb_sel),
        .o_wb_rdt(wb_rdt),
        .o_wb_ack(wb_ack),
        .o_gpio(GPIO)
    );

endmodule