[project]
name                = modem
version             = 0.1
out_dir             = out
build_dir           = build

[server]
hostname            = localhost
port                = 2020
privkey             = /home/joppe/.ssh/id_rsa
pubkey              = /home/joppe/.ssh/id_rsa.pub

[target.synth]
toolchain           = ISE
ise_settings        = /opt/packages/xilinx/14.7/ISE_DS/settings64.sh
# Toolchain settings
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
toplevel            = top_generic
xst_opts            = -vlgincdir rtl
#ngdbuild_opts      =
#map_opts           =
#par_opts           =
#netgen_opts        =
#bitgen_opts        =
#trce_opts          =
# Files
#files_vhdl          = 
files_verilog       = rtl/toplevel/top_generic.v
                      rtl/core/nco_q15.v
                      rtl/core/sigmadelta_sampler.v
                      rtl/arch/spartan-6/lvds_comparator.v
files_con           = boards/mimas_v1/constraints.ucf
files_other         = rtl/util/conv.vh

[target.serv]
toolchain           = iverilog
runtime             = all
toplevel            = tb_serving
ivl_opts            = -Irtl
files_verilog       = external/serv/rtl/serv_aligner.v
                      external/serv/rtl/serv_alu.v
                      external/serv/rtl/serv_bufreg.v
                      external/serv/rtl/serv_bufreg2.v
                      external/serv/rtl/serv_compdec.v
                      external/serv/rtl/serv_csr.v
                      external/serv/rtl/serv_ctrl.v
                      external/serv/rtl/serv_debug.v
                      external/serv/rtl/serv_decode.v
                      external/serv/rtl/serv_immdec.v
                      external/serv/rtl/serv_mem_if.v
                      external/serv/rtl/serv_rf_if.v
                      external/serv/rtl/serv_rf_ram_if.v
                      external/serv/rtl/serv_rf_ram.v
                      external/serv/rtl/serv_rf_top.v
                      external/serv/rtl/serv_state.v
                      external/serv/rtl/serv_synth_wrapper.v
                      external/serv/rtl/serv_top.v
                      external/serv/servile/servile_arbiter.v
                      external/serv/servile/servile_mux.v
                      external/serv/servile/servile_rf_mem_if.v
                      external/serv/servile/servile.v
                    #   external/serv/serving/serving_ram.v
                      sim/overrides/serving_ram.v
                      external/serv/serving/serving.v
                      sim/tb/tb_serving.v

[target.sim]
toolchain           = iverilog
runtime             = all
toplevel            = tb_nco_q15
ivl_opts            = -Irtl
#vvp_opts            =
# Files
#files_sysverilog    = 
files_verilog       = sim/tb/tb_nco_q15.v
                      rtl/core/nco_q15.v
                      rtl/core/lvds_comparator.v
                      sim/overrides/sigmadelta_sampler.v
files_other         = rtl/util/conv.vh