`timescale 1ns/1ps

module soclet #(
    parameter memfile = "",
    parameter memsize = 8192,
    parameter sim = 1'b0
)(
    input wire i_clk,
    input wire i_rst,

    input wire [31:0] i_GPI_A,
    input wire [31:0] i_GPI_B,
    input wire [31:0] i_GPI_C,
    input wire [31:0] i_GPI_D,

    output wire [31:0] o_GPO_A,
    output wire [31:0] o_GPO_B,
    output wire [31:0] o_GPO_C,
    output wire [31:0] o_GPO_D
);

    wire [31:0] wb_adr;
    wire [31:0] wb_dat;
    wire [31:0] wb_rdt;
    wire [3:0] wb_sel;
    wire wb_we;
    wire wb_stb;
    wire wb_ack;

    wire [4*32-1:0] GPO;
    wire [4*32-1:0] GPI;
    assign o_GPO_A = GPO[32*1-1:32*0];
    assign o_GPO_B = GPO[32*2-1:32*1];
    assign o_GPO_C = GPO[32*3-1:32*2];
    assign o_GPO_D = GPO[32*4-1:32*3];
    assign GPI[32*1-1:32*0] = i_GPI_A;
    assign GPI[32*2-1:32*1] = i_GPI_B;
    assign GPI[32*3-1:32*2] = i_GPI_C;
    assign GPI[32*4-1:32*3] = i_GPI_D;

    serving #(
        .memfile(memfile),
        .memsize(memsize),
        .sim(sim),
        .RESET_STRATEGY("MINI"),
        .WITH_CSR(1)
    ) serv (
        .i_clk(i_clk),
        .i_rst(i_rst),
        .i_timer_irq(1'b0),
        .i_wb_rdt(wb_rdt),
        .i_wb_ack(wb_ack),
        .o_wb_adr(wb_adr),
        .o_wb_dat(wb_dat),
        .o_wb_sel(wb_sel),
        .o_wb_we(wb_we),
        .o_wb_stb(wb_stb)
    );

    wb_gpio_banks #(
      .BASE_ADDR(32'h40000000),
      .NUM_BANKS(4)
    ) gpio (
        .i_wb_clk(i_clk),
        .i_wb_rst(i_rst),
        .i_wb_dat(wb_dat),
        .i_wb_adr(wb_adr),
        .i_wb_we(wb_we),
        .i_wb_stb(wb_stb),
        .i_wb_sel(wb_sel),
        .i_gpio(GPI),
        .o_wb_rdt(wb_rdt),
        .o_wb_ack(wb_ack),
        .o_gpio(GPO)
    );

endmodule