`timescale 1ns/1ps

module top_generic(
    input wire aclk,
    input wire aresetn,

    output wire led_green,
    output wire led_red,

    output wire[5:0] r2r
);

    `include "core/nco_q15_funcs.vh"

    assign led_green = 1'b0;
    assign led_red = 1'b0;

    wire [15:0] sin_q15;
    wire clk_en;
    nco_q15 #(
        .CLK_HZ(100_000_000),
        .PHASE_BITS(16)
    ) nco (
        .clk    (aclk),
        .rst_n  (aresetn),
        .ftw_in (32'h0),
        .ftw_we (1'b0),
        .sin_q15(sin_q15),
        .cos_q15(),
        .clk_en (clk_en)
    );

    // sin_q15: signed Q15 in [-32768, +32767]
    wire signed [15:0] s = sin_q15;
    // Bias to 0..65535 and round before downscaling by 1024 (>>10)
    wire [16:0] biased = s + 17'sd32768;           // 0..65535
    wire [5:0] dac_code_next = biased[15:10];     // 0..63 (MSB=bit5)
    // Register it at the sample rate (clk_en)
    reg [5:0] dac_code;
    always @(posedge aclk or negedge aresetn) begin
        if (!aresetn) dac_code <= 6'd0;
        else if (clk_en) dac_code <= dac_code_next;
    end
    assign r2r = dac_code;
endmodule