[project]
name                = modem
version             = 0.1
out_dir             = out
build_dir           = build

[target.ip]
toolchain           = ISE_IP
ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
files_def           = boards/mimas_v1/ip/clk_gen.xco

[target.synth]
toolchain           = ISE
ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
toplevel            = top_generic
xst_opts            = -vlgincdir rtl/util
files_verilog       = rtl/toplevel/top_generic.v
                      rtl/util/conv.vh
                      rtl/core/nco_q15.v
                      rtl/core/sigmadelta_sampler.v
                      rtl/core/sigmadelta_rcmodel_q15.v
                      rtl/core/sigmadelta_input_q15.v
                      rtl/core/mul_const.v
                      rtl/core/lpf_iir_q15_k.v
                      rtl/core/decimate_by_r_q15.v
                      rtl/core/mcu_peripherals.v
                      rtl/core/mcu.v
                      rtl/core/mem_jtag_writable.v
                    # Arch
                      rtl/arch/spartan-6/lvds_comparator.v
                      rtl/arch/spartan-6/clk_gen.v
                      rtl/arch/spartan-6/jtag_if.v
                    # SERV
                      rtl/serv/serv_aligner.v
                      rtl/serv/serv_alu.v
                      rtl/serv/serv_bufreg.v
                      rtl/serv/serv_bufreg2.v
                      rtl/serv/serv_compdec.v
                      rtl/serv/serv_csr.v
                      rtl/serv/serv_ctrl.v
                      rtl/serv/serv_debug.v
                      rtl/serv/serv_decode.v
                      rtl/serv/serv_immdec.v
                      rtl/serv/serv_mem_if.v
                      rtl/serv/serv_rf_if.v
                      rtl/serv/serv_rf_ram_if.v
                      rtl/serv/serv_rf_ram.v
                      rtl/serv/serv_state.v
                      rtl/serv/serv_rf_top.v
                      rtl/serv/serv_synth_wrapper.v
                      rtl/serv/serv_top.v
                    # QERV
                    #   rtl/qerv/serv_rf_top.v
                    #   rtl/qerv/serv_synth_wrapper.v
                    #   rtl/qerv/serv_top.v
                    #   rtl/qerv/qerv_immdec.v
                    # Servile
                      rtl/serv/servile_arbiter.v
                      rtl/serv/servile_mux.v
                      rtl/serv/servile_rf_mem_if.v
                      rtl/serv/servile.v
                    #   rtl/qerv/servile_arbiter.v
                    #   rtl/qerv/servile_mux.v
                    #   rtl/qerv/servile_rf_mem_if.v
                    #   rtl/qerv/servile.v
                    # WB
                      rtl/wb/wb_gpio.v
                      rtl/wb/wb_gpio_banks.v
                      rtl/wb/wb_mux.v
                      rtl/wb/jtag_wb_bridge.v
                      rtl/wb/wb_timer.v

files_con           = boards/mimas_v1/constraints.ucf
files_other         = rtl/util/rc_alpha_q15.vh
                      rtl/util/clog2.vh
                      sw/sweep/sweep.hex

[target.synth_sim]
toolchain           = iverilog
runtime             = all
toplevel            = tb_top_generic
ivl_opts            = -Irtl/util
files_verilog       = rtl/toplevel/top_generic.v
                      rtl/util/conv.vh
                      rtl/core/nco_q15.v
                      rtl/core/sigmadelta_sampler.v
                      rtl/core/sigmadelta_rcmodel_q15.v
                      rtl/core/sigmadelta_input_q15.v
                      rtl/core/mul_const.v
                      rtl/core/lpf_iir_q15_k.v
                      rtl/core/decimate_by_r_q15.v
                      rtl/core/mcu_peripherals.v
                      rtl/core/mcu.v
                      rtl/core/mem_jtag_writable.v
                    # Arch
                      rtl/core/lvds_comparator.v
                      sim/overrides/clk_gen.v
                      rtl/core/jtag_if.v
                    # SERV
                      rtl/serv/serv_aligner.v
                      rtl/serv/serv_alu.v
                      rtl/serv/serv_bufreg.v
                      rtl/serv/serv_bufreg2.v
                      rtl/serv/serv_compdec.v
                      rtl/serv/serv_csr.v
                      rtl/serv/serv_ctrl.v
                      rtl/serv/serv_debug.v
                      rtl/serv/serv_decode.v
                      rtl/serv/serv_immdec.v
                      rtl/serv/serv_mem_if.v
                      rtl/serv/serv_rf_if.v
                      rtl/serv/serv_rf_ram_if.v
                      rtl/serv/serv_rf_ram.v
                      rtl/serv/serv_state.v
                      rtl/serv/serv_rf_top.v
                      rtl/serv/serv_synth_wrapper.v
                      rtl/serv/serv_top.v
                    # QERV
                    #   rtl/qerv/serv_rf_top.v
                    #   rtl/qerv/serv_synth_wrapper.v
                    #   rtl/qerv/serv_top.v
                    #   rtl/qerv/qerv_immdec.v
                    # Servile
                      rtl/serv/servile_arbiter.v
                      rtl/serv/servile_mux.v
                      rtl/serv/servile_rf_mem_if.v
                      rtl/serv/servile.v
                    #   rtl/qerv/servile_arbiter.v
                    #   rtl/qerv/servile_mux.v
                    #   rtl/qerv/servile_rf_mem_if.v
                    #   rtl/qerv/servile.v
                    # WB
                      rtl/wb/wb_gpio.v
                      rtl/wb/wb_gpio_banks.v
                      rtl/wb/wb_mux.v
                      rtl/wb/jtag_wb_bridge.v
                      rtl/wb/wb_timer.v

                      sim/tb/tb_top_generic.v

files_con           = boards/mimas_v1/constraints.ucf
files_other         = rtl/util/rc_alpha_q15.vh
                      rtl/util/clog2.vh
                      rtl/util/conv.vh
                      sw/sweep/sweep.hex

[target.jtag]
toolchain           = ISE
ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
toplevel            = top_jtag
xst_opts            = -vlgincdir rtl/util -keep_hierarchy yes
files_other         =
files_con           = boards/mimas_v1/constraints.ucf
files_verilog       = rtl/arch/spartan-6/jtag_if.v
                      rtl/arch/spartan-6/clk_gen.v
                      rtl/wb/jtag_wb_bridge.v
                      rtl/wb/wb_gpio.v
                      rtl/toplevel/top_jtag.v

[target.svftest]
toolchain           = iverilog
runtime             = all
toplevel            = tb_svf
files_verilog       = sim/tb/tb_svf.v
                      sim/overrides/jtag_if.v
                      rtl/core/cdc_strobed.v
files_other         = sim/other/test.svf

[target.tb_wb_timer]
toolchain           = iverilog
runtime             = all
toplevel            = tb_wb_timer
files_verilog       = sim/tb/tb_wb_timer.v
                      rtl/wb/wb_timer.v

[target.tools]
toolchain           = make
output_files        = tools/test
buildroot           = tools
files_makefile      = tools/Makefile
files_other         = tools/digilent_jtag.cpp
                      tools/digilent_jtag.hpp
                      tools/argparse.cpp
                      tools/argparse.hpp
                      tools/test.cpp