//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.12 
//Created Time: 2025-10-01 16:50:37
create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]
create_clock -name CLK_120 -period 8.333 -waveform {0 4.167} [get_nets {clk_120}]
create_clock -name CLK_15 -period 66.666 -waveform {0 33.333} [get_nets {clk_15}]